• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.151-156
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• 1999

본 논문에서는 국제 표준화기구(ISO) 산하의 동영상 전문가 그룹(MPEG)의 오디오 압축방법들중 하나인 MPEG-I layer 3 의 복호화기를 고정 소수점으로 변환한 후, $OakDSPCore^{\circledR}$를 기반으로 전 과정을 어셈블리어로 실시간 구현하였다. 실시간 구현에 사용된 $OakDSPCore^{\circledR}$는 DSP Group사에서 개발된 저전력 소비형 16-비트 고정 소수점 DSPCore로서 40MIPS의 성능을 가지고 있으며, 음성/오디오, 통신, 디지털 셀룰라폰 같은 소비자의 맞게 ASIC화할 수 있는 장점을 가지고 있다. 구현된 MP3 복호화기는 약33 MIPS의 복잡도를 나타내며, 사용된 메모리양은 프로그램 ROM 3.1K words, 데이터 ROM(table) 10.82K words 및 ROM 6.1K words이다. 구현된 MP3 복호화기는 OMNI-MEDIASOUND에서 제공하는 4개의 test 벡터들을 bit-exact하게 통과하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.167-170
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• 2001

본 논문에서는 미국에서 고 선명(High Definition) TV를 위한 오디오 표준인 ATSC에 의해서 채택되고, DVD의 오디오 코덱으로 널리 채택된 Dolby AC-3 복호화기를 고정 소수점으로 변환한 후, ARM929T를 기반으로 실시간 구현하였다. 실시간 구현에 사용된 ARM920T 는 저전력 소비형 32-비트 고정 소수점 RISC 구조이며, 명령어 Cache 와 데이터 Cache, MMU(Memory Management Unit)로 구성되어 있다. 그리고 200MIPS 의 성능을 가지고 있어, 음성/오디오, 통신, 디지털 셀룰라폰에 적용할 수 있고, ASIC 화 할 수 있는 장점을 가지고 있다. 구현된 AC-3 복호화기는 약 67MIPS(6 채널, 640kbps, 48KHz)의 복잡도를 나타내며, 사용된 메모리양은 프로그램 ROM 23.3K Bytes, 데이터 ROM(table) 4.62K Bytes 및 RAM 45K Bytes 이다. 구현된 AC-3 복호화기는 Dolby사에서 제공하는 40 개의 test 벡터들을 bit-exact하게 통과하였다.

• Broadcasting and Media Magazine
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• v.24 no.4
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• pp.120-131
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• 2019

고해상도 영상 서비스 증가와 Youtube, Netflix와 같은 OTT 중심의 동영상 시청 환경 변화에 따라, 기존 대비 높은 압축률을 목표로 하는 새로운 비디오 코덱 표준들이 활발히 개발되고 있다. 그 중 가장 대표적인 것은 MPEG에서 개발 중인 VVC(Versatile Video Coding)로 기존 HEVC(High Efficiency Video Coding) 대비 2배의 압축률 달성을 목표로 하고 있다. 하지만 압축률 향상을 위한 새로운 부호화 도구들의 복잡도가 점점 증가함에 따라, 하드웨어 복호화기 구현시 많은 어려움이 있을 것으로 예상된다. VVC 표준화에서는 이런 어려움을 극복하기 위하여, 하드웨어 구현 관점에서 부호화 도구들을 최적화하고 이를 사용함에 있어 몇가지 제약들을 정의하고 있다. 본 논문에서는 현재 VVCCD 및 VTM 6.0 소프트웨어 기준으로 하드웨어 복호화기 구현을 고려하여 채택된 부호화 도구 및 제약에 대하여 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.79-89
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• 2011

Recent development of embedded processors makes it possible to play back video contents in real-time on portable devices. Because of their limited battery capacity and low computational performance, however, portable devices still have significant problems in real-time decoding of high quality or high resolution compressed video. Although previous approaches are successful in achieving complexity-scalable decoder by controlling computational complexity of decoding elements, they cause significant objective quality loss coming from mismatch between encoder and decoder. In this paper, we propose a selective B slice skip-decoding method to implement a low complexity video decoder. The proposed method performs selective skip decoding process of B slice which satisfies the proposed conditions. The skipped slices are reconstructed by simple reconstruction method utilizing adjacent reconstructed pictures. Experimental result shows that proposed method not only reduces computational complexity but also maintains subjective visual quality.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.32-43
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• 2010

This paper presents deblocking filter for low-complexity video decoder. Baseline profile of the H.264/AVC used for mobile devices such as mobile phones has two times higher compression performance than the MPEG-4 Visual but it has a problem of serious complexity as using 1/4-pel interpolation filter, adaptive entropy model and deblocking filter. This paper presents low-complexity deblocking filter for decreasing complexity of decoder with preserving the coding efficiency of the H.264/AVC. In this paper, the proposed low-complexity deblocking filter decreased 49% of branch instruction than conventional approach as calculating value of BS by using the CBP. In addition, a range of filtering of strong filter applied in intra macroblock boundaries was limited to two pixels. According to the experimental results, the proposed low-complexity deblocking filter decreased -0.02% of the BDBitrate comparison with baseline profile of the H.264/AVC, decreased 42% of the complexity of deblocking filter, and decreased 8.96% of the complexity of decoder.

• Journal of Broadcast Engineering
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• v.20 no.1
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• pp.171-182
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• 2015

HEVC can increase the coding efficiency significantly compared with H.264/AVC however it requires much larger computational complexities in both encoder and decoder. In this paper, the decision process of inter-prediction modes in the HEVC reference software has been studied and a fast algorithm to reduce the computational complexity of encoder and decoder is introduced. The proposed scheme introduces a early decision criteria using the outputs of uni-directional predictions to skip the bi-directional prediction estimation. From the experimental results, it was proven that the proposed method can reduce the encoding complexity by 12.0%, 14.6% and 17.2% with 0.6%, 1.0% and 1.5% of coding efficiency penalty, respectively. In addition, the ratio of bi-directional prediction mode was reduced by 6.3%, 11.8% and 16.6% at the same level of coding efficiency penalty, respectively, which should lead to the decoder complexity reduction. Finally, the effects of the proposed scheme are maintained regardless of the use of the early skip decision algorithm which is implemented in the HEVC reference software.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.6
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• pp.66-74
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• 2010

Recently distributed video coding (DVC) is spotlighted for the environment which has restriction in computing resource at encoder. Wyner-Ziv (WZ) coding is a representative scheme of DVC. The WZ encoder independently encodes key frame and WZ frame respectively by conventional intra coding and channel code. WZ decoder generates side information from reconstructed two key frames (t-1, t+1) based on temporal correlation. The side information is regarded as a noisy version of original WZ frame. Virtual channel noise can be removed by channel decoding process. So the performance of WZ coding greatly depends on the performance of channel code. Among existing channel codes, Turbo code and LDPC code have the most powerful error correction capability. These channel codes use stochastically iterative decoding process. However the iterative decoding process is quite time-consuming, so complexity of WZ decoder is considerably increased. Analysis of the complexity of LPDCA with real video data shows that the portion of complexity of LDPCA decoding is higher than 60% in total WZ decoding complexity. Using the HDA (Hard Decision Aided) method proposed in channel code area, channel decoding complexity can be much reduced. But considerable RD performance loss is possible according to different thresholds and its proper value is different for each sequence. In this paper, we propose an adaptive HDA method which sets up a proper threshold according to sequence. The proposed method shows about 62% and 32% of time saving, respectively in LDPCA and WZ decoding process, while RD performance is not that decreased.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2465-2473
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• 2012

Recently, as one of low complexity video encoding methods, DVC (Distributed Video Coding) scheme has been actively studied. Most of DVC schemes exploit feedback channel to achieve better coding performances, however, this causes these schemes to have high decoding delay. In order to overcome these, this paper proposes a new fast DVC decoding method using parity-bit request model, which can be obtained by using bit-error rate, sent by encoder with motion vector, which is transmitted through feedback channel by decoder after generating side information. Through several simulations, it is shown that the proposed method improves greatly the decoding speed, compared to the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.58-66
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• 2009

Recently the emerging demands of the light-video encoder promotes lots of research efforts on DVC (Distributed Video Coding). As an appropriate video compression method, DVC has been studied, and Wyner-Ziv (WZ) video compression is its one representative structure. The WZ encoder splits the image into two kinds of frames, one is key frame which is compressed by conventional intra coding, and the other is WZ frame which is encoded by WZ coding. The WZ decoder decodes the key frame first, and estimates the WZ frame using temporal correlation between key frames. Estimated WZ frame (Side Information) cannot be the same as the original WZ frame due to the absence of the WZ frame information at decoder. As a result, the difference between the estimated and original WZ frames are regarded as virtual channel noise. The WZ frame is reconstructed by removing noise in side information. Therefore precise noise estimation produces good performance gain in WZ video compression by improving error correcting capability by channel code. But noise cannot be estimated precisely at WZ decoder unless there is good WZ frame information, and generally it is estimated from the difference of corresponding key frames. Also the estimated noise is limited by comparing with frame level noise to reduce the uncertainty of the estimation method. However these methods cannot provide good noise estimation for every frame or each bit plane. In this paper, we propose a noise nodel selection method which chooses a better noise model for each bit plane after generating candidate noise models. Experimental result shows PSNR gain up to 0.8 dB.