• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.6
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• pp.79-89
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• 2004

Fingerprint identification consists of user enrollment phase storing user's fingerprint in a database and user identification phase making a candidate list for a given fingerprint. straightforward approach to perform the user identification phase is to scan the entire database sequentially, and takes times for large-scale databases. In this paper, we develop a hardware design which can perform the user identification phase in real-time. Our design employs parallel processing techniques and has been implemented on a PCI-based platform containing an FPGA and SDRAMs. Based on the performance evaluation, our hardware implementation can provide a scalability and perform the fingerprint identification in real-time.

• Journal of Engineering Education Research
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• v.26 no.3
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• pp.35-41
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• 2023

The study was conducted to develop two parallel short forms for the Convergent thinking and Problem solving questionnaires which are part of H University's core competency diagnostic tools, based on Multi-Item Response Theory. Item responses of 2,580 students were analyzed using Graded Response Model(GRM) to determine item difficulty and discrimination of each item. The research results are as follows. Two parrallel short tests were developed for the Convergent thinking questionnaire consisting of 12 items which were originally 17 items. Likewise, the Problem solving questionnaire, which originally consisted of 15 questions, was divided into two parallel short forms, each consisting of 9 items. The reliability of the shortened parallel tests was confirmed through internal consistency analysis, and their similarity to the original tests was established through correlation analysis. This study contributed to quality management of competency-based education and programs at H University by developing shortened tests. Based on the results, implications were presented as well as limitations and discussions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1198-1205
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• 2000

In this paper, we introduce a modified interference cancellation scheme to overcome MAI in DS-CDMA. Among ICs(Interference Cancellers), PIC(Parallel IC) requires the more complexity, and SIC(Successive IC) faces the problems of the long delay time. Most of all, the adaptive detector achieves the good BER performance using the adaptive Inter conducted iteration algorithm. So it requires many iterations. To resolve the problems of them, we propose an improved adaptive detector that the received signal removed MAI through the sorting scheme and the cancellation method are fed into the adaptive filter. Because the improved input signal is fed into the adaptive filter, it has the same BER performance only using smaller iterations than the conventional adaptive detector, and the proposed detector having adaptive filter requires less complexity than the other detectors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2B
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• pp.138-143
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• 2003

One of the important design issues for IP routers responsible for packet forwarding in computer networks is the route-lookup mechanism. For each incoming packet, IP routing requires that a router performs a longest-prefix-match address lookup in order to determine the next hop that the incoming packet should be forwarded to. In this paper, we present a new scheme which applies the hashing function for IP address lookup. In the proposed scheme, the forwarding table is composed of multiple SRAMs, and each SRAM represents an address lookup table in each prefix. Hashing function is applied in order to find out the matching entries from the address lookup tables in parallel, and the entry with the longest prefix match among them is selected. Simulation using the MAE-WEST router example shows that a large routing table with 37000 entries can be compacted to a forwarding table of 300 Kbytes in the proposed scheme. It is also shown that the proposed scheme achieves one route lookup every 1.93 memory accesses in average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.751-762
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• 2004

In this paper, we propose the method to derive new GRM(Generalized Reed-Muller) coefficients for each 2$^n$ polarities using Triangle cell. As the existing methods to generate GRM coefficients, there are Green's method to operate transform matrix with a given RM coefficient and Besslich's method to get other polarities using basic transfer matrices repeatedly. In this paper, Triangle cell is defined so as to obtain GRM coefficients efficiently. After arranging 2$^n$ given RM coefficients of a first row of Triangle cell, sequence modulo sum is peformed in parallel to low column by a fixed numerical formula. To prove the efficiency of proposed arithmetic method, it is compared with Besslich’s method. As the compared result, to calculate GRM coefficients of all polarities to n input variables, Besslich’s method needs 2$^n$$^{-1}$ ${\times}$(2$^n$-1) two-input Ex-ORs and the proposed method needs 2${\times}$(the number of Ex-ORs for n-1 variables)+3$^n$$^{-1}$ for the same system complexity - (lo $g_2$$^n$) $T_{X}$./.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.230-238
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• 2005

An orthogonal frequency division multiplexing (OFDM) system consists of a number of independently modulated subcarriers and, thus, a high peak-to-average power ratio (PAR) can occur when the subcarriers are added coherently. The high PAR brings such disadvantages as an increased complexity of the analog-to-digital (ADC) and digital-to-analog (DAC) converters and a reduced efficiency of the radio frequency (RF) power amplifier. In this paper, we propose a novel PAR reduction scheme called selective mapping of partial tones (SMOPT). The SMOPT scheme has a reduced complexity, lower sensitivity to peak reduction tones (PRT) positions, and a shorter processing time as compared with the conventional tone reservation (TR) scheme. The performance of the SMOPT scheme is analyzed based on the IEEE 802.1la wireless local area network(WLAM) physical layer model. Numerical results show that the SMOPT scheme outperforms the TR scheme under various scenarios.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2823-2834
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• 1998

This paper deals with the problem of one-to-one mapping of $2^n$ task modules of a parallel program to an n-dimensional hypercube multicomputer so as to minimize to total communication cost during the execution of the task. The problem of finding an optimal mapping has been proven to be NP-complete. We first propose a graph modification technique which transfers the mapping problem in a hypercube multicomputer into the problem of finding a set of maximum cutsets on a given task graph. Using the graph modification technique, we then propose a repeated mapping scheme which efficiently finds a one-to-one mapping of task modules to a hypercube multicomputer by repeatedly applying an existing bipartitioning algorithm on the modified graph. The repeated mapping scheme is shown to be highly effective on a number of test task graphs, it increasingly outperforms the greedy and recursive mapping algorithms as the number of processors increase. The proposed algorithm is shown to be very effective for regular graph, such as hypercube-isomorphic or 'almost' isomorphic graphs and meshes; it finds optimal mapping on almost all the regular task graphs considered.