• Proceedings of the Korea Water Resources Association Conference
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• 2018.05a
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• pp.278-278
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• 2018

현재 우리나라에서는 행정안전부의 풍수해저감종합계획, 사전재해영향성검토협의, 재해위험지구개선사업 등에 해외에서 개발된 상용프로그램이 사용돼 접근성 저하로 인해 지자체 방재담당자의 실무나 대학에서 연구용으로 다루기에는 한계가 있다. 이에 본 연구에서는 내수침수, 외수침수, 2차원 침수해석으로 구성하여 GUI 기능을 강화한 통합침수재해지도 작성시스템(i-FIM, Integrated Flood Inundation Modeling system)을 개발하여 입력자료의 구성 및 매개변수의 수정이 용이하게 함으로써 하수관망 등에 부분적인 설계 변경이 있는 경우 지자체 방재담당자가 간단한 작업을 통해 침수영향 변화를 쉽게 파악할 수 있도록 하였다. 또한, 상세한 지형의 반영이 필요한 도시지역의 2차원 침수해석의 경우 계산격자 망의 크기가 작아질수록 소요되는 계산시간이 기하급수적으로 증가하는 한계가 있어 i-FIM에서는 계산격자를 $2{\times}2$, $3{\times}3$, $5{\times}5$ Subgrid 형태의 격자를 적용하고, 병렬프로그래밍과 계산시간조정 기능을 추가하여 2차원 침수해석 모형의 계산 속도를 향상시켰다. 이를 실무에 적용하기 앞서 2006년 집중호우로 인해 안성시에서 발생한 제방 붕괴사상, 2016년 태풍 차바로 인해 울산시에서 발생한 제방 월류 사상을 통해 침수흔적도와 비교하여 검증을 실시하였다. i-FIM에서 최종적인 2차원 침수해석 결과는 2017년에 개정된 '재해지도 작성 기준 등에 관한 지침'의 침수심 등급 구분의 색채 설정에 따라 각 격자별 침수심을 표출함으로써 표준화된 재해지도 작성이 가능하도록 하였다. 또한, 포털사이트의 지도 및 위성지도에 표출함으로써 침수 위험이 발생할 수 있는 지역의 현재 이용 용도를 파악하여 침수재해에 대한 상세한 대책을 마련할 수 있을 것으로 판단된다.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.440-451
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• 2019

We propose a system that allows three dimensional manipulation of face in video. The 3D face manipulation of the proposed system overlays the 3D face model with the user 's manipulation on the face region of the video frame, and it allows 3D manipulation of the video in real time unlike existing applications or methods. To achieve this feature, first, the 3D morphable face model is registered with the image. At the same time, user's manipulation is applied to the registered model. Finally, the frame image mapped to the model as texture, and the texture-mapped and deformed model is rendered. Since this process requires lots of operations, parallel processing is adopted for real-time processing; the system is divided into modules according to functionalities, and each module runs in parallel on each thread. Experimental results show that specific parts of the face in video can be manipulated in real time.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.3
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• pp.27-38
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• 1999

We study on the security for the block ciphers with 20block structure which have provable security against DC and LC on the view point of higher order DC, 2-block structures are classified three types according to the location of round function such as C(Center)-type R(Right)-type and L(Left)-type We prove that in the case of 4 rounds encryption function these three types provide the equal strength against higher order DC and that in the case of 5 or more rounds R-type is weaker than C-type and L-type.

• KNOM Review
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• v.22 no.1
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• pp.60-67
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• 2019

Graphical Processing Units(GPUs) achieve high performance undertaking from relatively uniformed computation in parallel. The technology related to General Purpose GPU(GPGPU) has been enhanced, which provides concurrent kernel execution of multi and diverse applications at the same time, but it is still limited to support resource sharing or planning. NVIDIA recently introduces Multi-Process Service(MPS), which allows kernels from different applications can be execute concurrently. However, the strength of MPS comes along with the characteristics of applications and the order of their execution. This paper shows the performance analysis of diverse scientific applications in real world. Based on the analysis, we prove that it is important to the identify characteristics of co-run applications, and to schedule multiple applications via profiling to maximize MPS functionality.

• Journal of the Korean Society of Industry Convergence
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• v.26 no.6_2
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• pp.1097-1108
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• 2023

Recently, demand for technology for energy economy and stable supply is increasing due to the increase in power demand of loads. The amount of DC power generation using new and renewable energy is noticeably increasing, and the use of DC power supplies is also increasing due to the increase in electric vehicles and digital loads. During parallel operation to increase the capacity of the power converter, the module bus method or the method using Can communication and serial communication has significant difficulties in smooth operation due to communication time delay for information sharing. Synchronization of information sharing of each power converter is essential for smooth parallel operation, and minimization of communication time delay is urgently needed as a way to overcome this problem. In this paper, a new communication method using pulse width information is proposed as a communication method specialized for parallel operation of power converters to compensate for the disadvantage of communication transmission delay in the existing system. The proposed communication method has the advantage of being easily implemented using the PWM and Capture function of the microcomputer. In addition, the DC/DC converter for DC distribution was verified through simulation and experiment, and it has the advantage of easy capacity expansion when applied to parallel operation of various types of power converters as well as DC/DC converters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1047-1054
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• 2004

In this paper, we present two systolic arrays for computing multiplications in CF(2$\^$m/) generated by an irreducible all one polynomial (AOP). The proposed two systolic mays have parallel-in parallel-out structure. The first systolic multiplier has area complexity of O(㎡) and time complexity of O(1). In other words, the multiplier consists of m(m+1)/2 identical cells and produces multiplication results at a rate of one every 1 clock cycle, after an initial delay of m/2+1 cycles. Compared with the previously proposed related multiplier using AOP, our design has 12 percent reduced hardware complexity and 50 percent reduced computation delay time. The other systolic multiplier, designed for cryptographic applications, has area complexity of O(m) and time complexity of O(m), i.e., it is composed of m+1 identical cells and produces multiplication results at a rate of one every m/2+1 clock cycles. Compared with other linear systolic multipliers, we find that our design has at least 43 percent reduced hardware complexity, 83 percent reduced computation delay time, and has twice higher throughput rate Furthermore, since the proposed two architectures have a high regularity and modularity, they are well suited to VLSI implementations. Therefore, when the proposed architectures are used for GF(2$\^$m/) applications, one can achieve maximum throughput performance with least hardware requirements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.613-619
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• 2017

In this paper, DF(Dual Fuel) Generator modeling, which uses both conventional diesel fuel and LNG fuel, has been performed and monitoring system has been developed based on MATLAB/SIMULINK for the development of PMS(Power Management System) HILS(Hardware In the Loop Simulation). The principal components modeling of DF Generator are DF engine which provides the mechanical power and synchronous generator which convert the mechanical power into electrical power. Submodels, such as throttle body, intake manifold, torque generation and mass of LNG and diesel Quantity are used to perform DF engine. Also, governor is used for load sharing between paralleled DF generators to share a total load that exceeds the capacity of a single generator. To verify modeling of DF Generator designated ship lumped load Simulation is carried out. A validity of DF Generator has been verified by comparison between simulation results and estimated result from the designated lumped load.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.946-955
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• 2004

It is shown that the do Bruijn graph (dBG) can be used as an architecture for interconnection network and a suitable structure for parallel computation. Recent works have classified dBG based routing algorithms into shortest path routing and fault tolerant routing but investigation into fault free shortest path (FFSP) on dBG has been non-existent. In addition, as the size of the network increase, more faults are to be expected and therefore shortest path dBG algorithms in fault free mode may not be suitable routing algorithms for real interconnection networks, which contain several failures. Furthermore, long fault free path may lead to high traffic, high delay time and low throughput. In this paper we investigate routing algorithms in the condition of existing failure, based on the Bidirectional do Bruijn graph (BdBG). Two FFSP routing algorithms are proposed. Then, the performances of the two algorithms are analyzed in terms of mean path lengths and discrete set mean sizes. Our study shows that the proposed algorithms can be one of the candidates for routing in real interconnection networks based on dBG.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.19-25
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• 2009

In this thesis, design effective elimination interference algorithm of ICS repeat system for repeater that improve frequency efficiency. Error convergence speed and accuracy of LMS Algorithm are influenced by reference signal. For improve LMS Algorithm, suggest Adaptive channel estimate algorithm. For using channel characteristic, adaptive channel estimate algorithm make reference signal similar interference signal by convolution operation and complement LMS algorithm demerit. For make channel similar piratical channel, apply Jake's Rayleigh multi-path model that random five path with 130Hz Doppler frequency. LMS algorithm and suggested adaptive channel estimate algorithm that have 16 taps apply to ICS repeat system under Rayleigh multi-path channel, so simulate with MATLAB. According to simulate, ICS repeat system with LMS algorithm show -40dB square error convergent after 150 datas iteration and ICS repeat system with adaptive channel estimate algorithm show -80dB square error convergent after 200 datas iteration. Analyze simulation result, suggested adaptive channel estimate algorithm show more three times iteration performance than LMS algorithm, and 40dB accuracy.