• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.627-629
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• 2017

There are a lot of research results on the problem of finding the union and intersection of n rectangles on a plane. Lipski와 Preparata(1981) presented a sequential algorithm with O(nlogn) time and O(nlogn) space for the problem of finding the union of rectangles whose sides are parallel to the coordinate axes[1]. Alevizos(2013) presented an improved O(nlogn) time and O(n) space algorithm for the same problem[2]. In this paper, we consider the problem of finding the union of iso-oriented rectangles such that the intersection of them is not an empty set. In this case, the union of the rectangles becomes a connected area, that is, an orthogonal polygon. In this paper, we propose a parallel algorithm that solves this problem in constant time in a reconfigurable mesh(in short, RMESH) model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2031-2038
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• 2008

A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1095-1100
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• 2008

In a process of insect foot recognition, footprint segments as basic areas for recognition need to be extracted from scanned insect footprints and appropriate features should be found from the footprint segments in order to discriminate kinds of insects, because the characteristics of the features are important to classify insects. In this paper, we propose methods for automatic footprint segmentation and feature extraction. We use a Trace transform method in order to find out appropriate features from the extracted segments by the above methods. The Trace transform method builds a new type of data structure from the segmented images by functions using parallel trace lines and the new type of data structure has characteristics invariant to translation, rotation and reflection of images. This data structure is converted to Triple features by Diametric and Circus functions, and the Triple features are used for discriminating patterns of insect footprints. In this paper, we show that the Triple features found by the proposed methods are enough distinguishable and appropriate for classifying kinds of insects.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.5
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• pp.181-186
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• 2019

In order to reduce the fossil fuels consumed in conventional commercial independent diesel generators in the same environment as the island area, it is necessary to develop a photovoltaic system that will bear more than 40% of the independent system capacity. For this development, it is necessary to develop a high-capacity inverter that can improve the stability of the independent system installed in the island area and supply high-quality power to the load. In addition, the EMS power generation control system for the independent grid photovoltaic power generation system is a parallel operation power control system of the diesel generator connected with the solar power generation system. It controls the output of the diesel generator according to the load ratio and the solar power generation, A stable supply system is needed. This independent grid photovoltaic generation system can increase the solar power supply to the independent system area and increase the power stability of the independent system and further reduce the use of fossil fuel due to the ineffective power control of the independent system. It is expected that the economy will be secured early.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.401-406
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• 2021

Recently, mean-teacher models based on convolutional recurrent neural networks are popularly used in audio event detection. The mean-teacher model is an architecture that consists of two parallel CRNNs and it is possible to train them effectively on the weakly-labelled and unlabeled audio data by using the consistency learning metric at the output of the two neural networks. In this study, we tried to improve the performance of the mean-teacher model by using additional derivative features of the log-mel spectrum. In the audio event detection experiments using the training and test data from the Task 4 of the DCASE 2018/2019 Challenges, we could obtain maximally a 8.1% relative decrease in the ER(Error Rate) in the mean-teacher model using proposed derivative features.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.7
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• pp.977-985
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• 2021

The LiDAR sensor is attracting attention as a key sensor for autonomous driving vehicle. LiDAR sensor provides measured three-dimensional lengths within range using LASER. However, as much data is provided to the external system, it is difficult to process such data in an external system or processor of the vehicle. To resolve these issues, we develop integrated processing system for LiDAR sensor. The system is configured that client receives data from LiDAR sensor and processes data, server gathers data from clients and transmits integrated data in real-time. The test was carried out to ensure real-time processing of the system by changing the data acquisition, processing method and process driving method of process. As a result of the experiment, when receiving data from four LiDAR sensors, client and server process was operated using background or multi-core processing, the system response time of each client was about 13.2 ms and the server was about 12.6 ms.

• Smart Media Journal
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• v.8 no.3
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• pp.88-94
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• 2019

Livestock disease is a very important issue in the livestock industry because if livestock disease is not responded quickly enough, its damage can be devastating. To solve the issues involving the occurrence of livestock disease, it is necessary to diagnose in advance the status of livestock disease and develop systematic and scientific livestock feeding technologies. However, there is a lack of domestic studies on such technologies in Korea. This paper, therefore, proposes Livestock Disease Forecasting and Livestock Farm Integrated Control System using Cloud Computing to quickly manage livestock disease. The proposed system collects a variety of livestock data from wireless sensor networks and application. Moreover, it saves and manages the data with the use of the column-oriented database Hadoop HBase, a column-oriented database management system. This provides livestock disease forecasting and livestock farm integrated controlling service through MapReduce Model-based parallel data processing. Lastly, it also provides REST-based web service so that users can receive the service on various platforms, such as PCs or mobile devices.