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Serially Concatenated Space-Time Code using Iterative Decoding of High Data Rate Wireless Communication (고속 무선 통신을 위한 반복 복호 직렬 연쇄 시.공간 부호)

  • 김웅곤;구본진;양하영;강창언;홍대식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.4A
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    • pp.519-527
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    • 2000
  • This paper suggests and analyzes the Serially Concatenated Space-Time Code(SCSTC) with the possibility of a efficient high-speed transmission in a band limited channel. The suggested code has a structure that uses the interleaver to connect the space-time code as an inner code and the convolutional code as a outer code serially. This code keeps the advantage of high-speed transmission and also has the high BER performance. The performance of the suggested system is compared with the conventional bandwidth efficient trellis coded modulation, such as a Serially Concatenated Trellis Coded Modulation (SCTCM) and a Turbo-Trellis Coded Modulation(Turbo-TCM). The results show that the suggested system has a 2.8dB and 3dB better BER performance than SCTCM and Turbo-TCM respectively in case of the transmission rate 2b/s/Hz in fading channel.

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10Gbps Demultiplexer using SiGe HBT (SiGe HBT를 이용한 10Gbps 디멀티플렉서 설계)

  • 이상흥;강진영;송민규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.4A
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    • pp.566-572
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    • 2000
  • In the receiver of optical communication systems, a demultiplexer converts to a single data stream with a highbit rate into several parallel data streams with a low bit rate. In this paper, we design a 1:4 demultiplexer using SiGe HBT with emitter size of 2x8um² The operation speed is 10Gbps, the rise and fall times of 20-80% are37ps and 36ps, respectively and the dissipation of power is 1.40W.

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Data Intensive Cloud Service for Large Scientific Data Analysis (대규모 과학 데이터 분석을 위한 데이터 집약형 클라우드 서비스)

  • Hahm, Jae-Gyoon;Woo, Joon;Kim, Suk-Moon;Jang, Ji-Hoon;Park, Chan-Yeol
    • Proceedings of the Korean Information Science Society Conference
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    • 2012.06a
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    • pp.21-23
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    • 2012
  • 과학 연구에 있어서 데이터 집약형 컴퓨팅은 데이터의 대형화와 함께 그 중요성이 날로 더하여지고 있다. 데이터 집약형 컴퓨팅은 대용량 데이터의 분석을 통해 과학적 지식을 발견하는 것을 목적으로 하고 있으며, 그 처리 방법에 있어서 데이터 병렬화 기법을 주로 사용하게 되는데, 이는 클라우드 컴퓨팅을 통해 도움을 받을 수 있는 계산 처리 방식이다. 또 데이터 집약형 컴퓨팅 서비스에서는 데이터의 검색 및 추출, 전송 등에 있어서 대용량의 데이터를 다룰 수 있는 고도화된 기술을 필요로 하게 된다. 본 연구에서는 대규모 과학 데이터 분석을 위해서 필요한 연구 환경을 유연하고 확장성 있게 제공하는 데이터 집약형 클라우드 서비스를 제안하였다. 본 연구의 목표 시스템은 대량의 데이터 분석을 위해 필요한 다양한 형태의 플랫폼, 응용 프로그램, 시스템 프로그램 등을 제공하는 클라우드 기반의 분석 서비스와 데이터 속성에 기반하여 빠른 검색 및 추출, 효율적인 전송을 제공하는 데이터 서비스로 이루어진다.

Analysis of chaotic with lossless time-delayed chua's circuit (무손실 시간 지연을 갖는 Chua 회로에서의 카오스 해석)

  • 배영철;손영우;고윤석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.2
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    • pp.318-324
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    • 1997
  • Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, a linear resistor, and a nonlinear resistor. In this papre we analyze a circuit obtained by replacing the parallel LC resonator in the Chua's circuit by lossless transmission line. By using the method of characteristics of this circuit we show that various periodic motions and chaotic motions can the attained according to parameter variations. From Chua's circuit with a lossless transmission line a variely of chaotic attractors which are similar to those of the normal Chua's circuit are observed.

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NAWM Bus Architecture of High Performance for SoC (SoC를 위한 고성능 NAWM 버스 아키텍처)

  • Lee, Kook-Pyo;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.26-32
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    • 2008
  • The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

Design and Implementation of Cloud-based Sensor Data Management System (클라우드 기반 센서 데이터 관리 시스템 설계 및 구현)

  • Park, Kyoung-Wook;Kim, Kyong-Og;Ban, Kyeong-Jin;Kim, Eung-Kon
    • The Journal of the Korea institute of electronic communication sciences
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    • v.5 no.6
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    • pp.672-677
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    • 2010
  • Recently, the efficient management system for large-scale sensor data has been required due to the increasing deployment of large-scale sensor networks. In this paper, we propose a cloud-based sensor data management system with low cast, high scalability, and efficiency. Sensor data in sensor networks are transmitted to the cloud through a cloud-gateway. At this point, outlier detection and event processing is performed. Transmitted sensor data are stored in the Hadoop HBase, distributed column-oriented database, and processed in parallel by query processing module designed as the MapReduce model. The proposed system can be work with the application of a variety of platforms, because processed results are provided through REST-based web service.

Performance Comparison of Pilot Channel and Pilot Symbol Methods for DS/CDMA System (DS/CDMA 시스템에서 파일롯 채널방식과 파일롯 심볼방식의 성능비교)

  • Jeong, Sang-Wook;Shin, Seung-Hoon;Kwak, Kyung-Sup
    • Journal of IKEEE
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    • v.2 no.1 s.2
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    • pp.85-95
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    • 1998
  • We consider two methods for the pilot signal transmission in DS/CDMA systems: Pilot channel method which is parallel to the data channel and pilot symbol method which is serial to the data channel. In this paper, we analyze the two methods. The performance of the two methods is shown to be dependent upon the added noise, fading, pilot symbol period and pilot channel power. Through the analysis, it is found that the performance of the pilot symbol method outperforms compared to the pilot channel method.

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A High Performance Serial Protocol-P1355 (새로운 고성능 직렬접속 프로토콜 P1355의 표준화 동향)

  • Jun, Y.I.;Kang, S.M.;Han, W.Y.
    • Electronics and Telecommunications Trends
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    • v.9 no.4
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    • pp.23-34
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    • 1994
  • 직렬 접속 프로토콜은 두개 이상의 근거리 시스템간의 정보 교환에 사용된다. 현재까지 공식적인 기관에서 표준화되어 제정된 직렬 접속 규격들이 가지고 있는 성능은 전송 속도 측면에서 수 kbps에서 최대 10Mbps급에 한정되어 있는 관계로 수백 Mbps 혹은 수 Gbps급에 달하는 직렬 접속 프로토콜 성능을 요구하는 고성능 통신 및 정보 처리 시스템을 위한 새로운 직렬 접속 규격이 요구되고 있다. IEEE에서 표준화 작업중인 Multi-CPU 병렬 시스템을 위한 접속 규격인 P1355 접속 규격은 경제적이며 용이한 확장성을 가지는 칩과 칩간외에 보드와 보드간 혹은 랙과 랙간의 연결이 가능한 표준 규격안이다. P1355 접속 프로토콜은 특성이 서로 다른 DS, TS, HS link 규격들로 구성되어 있으며 이들은 선로 동작 속도 측면에서 각각 200Mbps, 250Mbps, 1Gbps의 성능을 가지고 있으며, 사용되는 데이터 심볼의 코딩 방식, 접속로 동작 초기화 및 오류 제어, 접속로의 물리적 성능 및 규격 등에서 차이를 가지고 있다. P1355는 일반적인 통신용 전송 선로에서 요구되는 물리 계층의 BER 성능보다 $10^5$에서 $10^10$배 향상된 선로 BER 특성과 이러한 하위 계층 특성을 바탕으로한 패킷 손실이 없는 간결한 상위계층 프로토콜을 특징으로 하며, 차세대 통신 수단인 ATM교환기 시스템의 서브 시스템 접속 규격으로 사용될 수 있다.

Design of Small-Size High-Power SPDT PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet Application (결함접지구조(Defected Ground Structure)를 갖는 휴대 인터넷용 소형 고전력 SPDT PIN 다이오드 스위치 설계)

  • Kim Dong-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.10 s.101
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    • pp.1003-1009
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    • 2005
  • In this paper, small-size high-power single pole double throw(SPDT) switch with defected pound structure(DGS) is presented for wireless broadband internet application. To reduce the circuit size using slow-wave characteristic, the DGS is applied to ${\lambda}/4$ transmission line of the switch and the measured results are compared with them of conventional switch. To secure high degree of isolation, the switch with the DGS is composed of shunt-connected PIN diodes and shows insertion loss of 0.8 dB and isolation more than 50 dB at 2.3 GHz. The size of the switch is reduced about $50\%$ only with the DGS patterns while it has very similar performance to the conventional shunt-type switch.

Design of RS Encoder/Decoder using Modified Euclid algorithm (수정된 유클리드 알고리즘을 이용한 RS부호화기/복호화기 설계)

  • Park Jong-Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.7
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    • pp.1506-1511
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    • 2004
  • The error control of digital transmission system is a very important subject because of the noise effects, which is very sensitive to transmission performance of the digital communication system It employs a modified Euclid's algorithm to compute the error-location polynomial and error-magnitude polynomial of input data. The circuit size is reduced by selecting the Modified Euclid's Algorithm with one Euclid Cell of mutual operation. And the operation speed of Decoder is improved by using ROM and parallel structure. The proposed Encoder and Decoder are simulated with ModelSim and Active-HDL and synthesized with Synopsys. We can see that this chip is implemented on Xilinx Virtex2 XC2V3000. A share of slice is 28%. nut speed of this paper is 45Mhz.