• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.5
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• pp.69-74
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• 2010

In this paper, we proposed a compact arbitrary dual-band band-stop filter using CRLH transmission line. The proposed filter used CRLH transmission line as stub and it developed dual-band band-stop characteristics using non-linear phase response of CRLH transmission line. The size of proposed filter is compact. And it can control arbitrary dual stop band. In this paper, designed band-stop filter at GPS band and ISM band As result, the S(2,1) is about -30dB at GPS band and about -29dB at ISM band. The fabricated filter is very compact. Its dimension is 10mm*15mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.6-7
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• 2019

본 논문에서는 양방향 전력 전송을 가능케 해주는 Dual-active-bridge (DAB) 컨버터에서, 고주파 변압기 대신 무선 전력 전송 코일을 이용한 시스템을 제안한다. 기존의 DAB 컨버터에서 주로 사용되는 고주파 변압기는 Core-type 또는 shell-type으로 만들어지며, 1차 측 권선과 2차 측 권선이 자기적으로 강하게 결합되어 높은 전력 전달 효율을 가지도록 만든다. 이런 DAB 컨버터를 직/병렬 연결해 MV-DC to LV-DC로 변환하는 반도체 변압기 등을 구성할 때, 1차 측 권선과 2차 측 권선 사이에는 절연 문제와 1차 측 스위치 회로와 2차 측 스위치 회로, 그리고 고주파 변압기가 각각 따로 절연해야 하는 문제점이 있다. 본 논문에서 제안하는 DAB 컨버터는 1차 측과 2차 측이 수 cm 이격되어 있어 1차 측과 2차 측 사이의 자기적 결합이 굉장히 약하다. 따라서 1차 측과 2차 측 코일을 커패시터로 공진시켜 전력을 전달하는 무선전력전송(Loosely Coupled Inductive Wireless Power Transfer)을 이용한다. 무선전력전송의 공진 topology는 Parallel-Series로 선택했고, impedance transformation 회로를 추가했다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.3-11
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• 2013

Recently, a plenty of researches have been conducted using the massively parallel processing of GPU for the implementation of communication system. In this paper, we tried to reduce software simulation time applying GPU with sliding block method to Viterbi decoder in DVB-T system which is one of European DTV standards. First of all, we implement DVB-T system by CPU and estimate cost time whereby the system processes one OFDM symbol. Secondly, we implement Viterbi decoder by software using NVIDIA's massive GPU processor. In our work, stream process method is applied to reduce the overhead for data transfer between CPU and GPU, as well as coalescing method to lower the global memory access time. In addition, data structure design method is used to maximize the shared memory usage. Consequently, our proposed method is approximately 11 times faster in 2K mode and 60 times faster in 8K mode for the process in Viterbi decoder.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1591-1592
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• 2006

이동 및 정보통신 시스템이 소형화 및 고성능화됨에 따라 System OR Package (SOP) 기술의 연구개발이 주목을 받고 있다. 저가형 SOP를 위하여 가장 많은 연구가 다층인쇄회로 기판에 수동소자 및 전송선로를 내장시키는 것이다. 본 논문에서는, 8층 KB 기판에 Meander line과 Radial/T Stub 패턴을 Advanced Design System(ADS) simulation을 이용하여 설계 및 제작하고 분석함으로써 정확한 SOP 디자인 및 설계 방향을 제시하고자 한다. 설계변수-패턴의 length, width, spacing, 각도와 공정변수-1층/3층, 기판 재질(prepreg(PP)과 resin coated copper(RCC))을 두어 제작하여 그 특성을 비교하였다. Meander Line는 PP보다 RCC에서의 인덕턴스가 크고 높은 자가 공진주파수를 가졌고, 3층보다 1층에서의 인덕턴스가 안정적이었다. Radial/T Stub는 PP보다 RCC에서의 커패시턴스가 작으나, 높은 자가 공진 주파수로 커패시턴스가 안정적이었다. Meander Line은 RCC, 병렬 전송선로 간격-400um, 병렬 전송선로 길이-500um, 1층 설계 시, 인덕턴스-1.60nH, 자가 공진주파수-9.21GHz 특성이 가장 우수하고, Radial Stub는 RCC, $60^{\circ}$, 1층 설계 시, 커패시턴스-0.62pF, 자가 공진주파수-9.06GHz의 특성이 나타났고, T Stub는 RCC, Stub 길이-600um, Stub 너비-150um, 1층 설계 시, 커패시턴스 -0.38pF, 자가 공진주파수-10GHz이상으로 우수한 특성을 나타냈다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.