• Title/Summary/Keyword: 병렬 스트림

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Design of InfiniBand RDMA-based Network Structure of Apache Storm (InfiniBand RDMA 기반 Apache Storm의 네트워크 구조 설계)

  • Yang, Seokwoo;Son, Siwoon;Choi, Seong-Yun;Choi, Mi-Jung;Moon, Yang-Sae
    • Proceedings of the Korea Information Processing Society Conference
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    • 2017.11a
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    • pp.679-681
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    • 2017
  • Apache Storm은 대용량 데이터 스트림을 처리하기 위한 실시간 분산 병렬 처리 프레임워크이며, 이를 사용해 다수의 프로세스 및 스레드를 동시에 동작시킬 수 있다. 하지만, 이러한 멀티 프로세스 및 스레드 환경을 제공하는 Storm은 많은 네트워크 시스템 호출을 수행하고, 이는 잦은 문맥 전환(context switch), 운영체제로의 버퍼 복사, 운영체제 내의 버퍼 복사 등으로 인해 CPU 과부하 문제를 발생시킬 수 있다. 이러한 문제는 고성능 네트워크 장비인 InfiniBand의 IPoIB(IP over InfiniBand) 통신을 사용할 때, InfiniBand가 지원하는 대역폭(bandwidth) 대비 저용량 데이터의 송수신으로 인해 더 잦은 문맥 전환과 버퍼 복사가 발생하여 CPU 과부하 문제가 더욱 심각해진다. 따라서, 본 논문에서는 InfiniBand의 RDMA(Remote Direct Memory Access)를 Storm에 적용하는 설계안을 제시함으로써 CPU 과부하 문제를 해결한다.

Implementation of GPU based MPEG-2 Decoder (GPU 기반의 MPEG-2 디코더의 구현)

  • Kim, Kyung-Su;Kim, Hong-Sik;Kim, Cheong-Ghil;Park, Woo-Chan
    • Journal of Digital Contents Society
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    • v.9 no.3
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    • pp.371-377
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    • 2008
  • Recently the performance of GPU is increasing much faster compared to GPU and GPU is used for various application programs. In this paper, MPEG-2 Decoder is implemented based on a GPU programming language, CG. The proposed methodology is to perform block rendering with texture data according to video standard with very high parallelism by using the pipeline of GPU which is a stream processing structure. To reduce the data bandwidth between system memory and GPU, local memory is used for graphic card. According to the experiment, the proposed scheme shows performance improvement by more than 2 times compared to CPU based scheme.

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GPU-based Shift-FFT Implementation for Ultra-High Resolution Hologram Generation (초고해상도 홀로그램 생성을 위한 GPU 기반 Shift-FFT 처리 구현)

  • Lee, Jaehong;Kang, Homin;Yeom, Han-ju;Cheon, Sanghoon;Park, Joongki;Kim, Duksu
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2020.07a
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    • pp.563-566
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    • 2020
  • 본 논문은 초고해상도 컴퓨터 홀로그램 생성을 위한 GPU 기반 2D Shift-FFT 의 효율적인 구현 방법을 제안한다. 본 연구가 제안하는 알고리즘은 기존에 여섯 단계로 이루어진 처리과정을 다섯 단계로 줄임으로서, 병렬처리에서 비효율적인 메모리 접근 과정을 줄인다. 또한, 핀드(pinned) 메모리 기반의 CPU-GPU 데이터 통신 통로인 핀드 버퍼(pinned buffer)를 사용하고 다중 스트림을 채용함으로써, GPU 활용의 주요 병목원인이 되는 데이터 통신의 부하를 줄이고 GPU 활용 효율을 높인다. 본 연구는 제안하는 알고리즘의 효용성을 증명하기 위해 서로 다른 두 시스템에 알고리즘을 구현하고, 다양한 크기의 행렬에 대한 2D-FFT 처리에 대한 성능을 측정하였다. 그 결과, CPU 기반의 FFTW 라이브러리 대비 최대 3 배, 동일한 GPU 를 사용하는 cuFFT 라이브러리 대비 최대 1.5 배 높은 성능을 달성하였다. 이러한 결과는, 본 연구가 제안하는 알고리즘의 효용성을 보여주는 결과다.

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Implementation of FFT on Massively Parallel GPU for DVB-T Receiver (DVB-T 수신기를 위한 대규모 병렬처리 GPU 기반의 FFT 구현)

  • Lee, Kyu Hyung;Heo, Seo Weon
    • Journal of Broadcast Engineering
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    • v.18 no.2
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    • pp.204-214
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    • 2013
  • Recently various research have been conducted relating to the implementation of signal processing or communication system by software using the massively parallel processing capability of the GPU. In this work, we focus on reducing software simulation time of 2K/8K FFT in DVB-T by using GPU. we estimate the processing time of the DVB-T system, which is one of the standards for DTV transmission, by CPU. Then we implement the FFT processing by the software using the NVIDIA's massively parallel GPU processor. In this paper we apply stream process method to reduce the overhead for data transfer between CPU and GPU, coalescing method to reduce the global memory access time and data structure design method to maximize the shared memory usage. The results show that our proposed method is approximately 20~30 times as fast as the CPU based FFT processor, and approximately 1.8 times as fast as the CUFFT library (version 2.1) which is provided by the NVIDIA when applied to the DVB-T 2K/8K mode FFT.

Multiplexing of UHDTV Based on MPEG-2 TS (MPEG-2 TS 기반의 UHDTV 다중화)

  • Jang, Euy-Doc;Park, Dong-Il;Kim, Jae-Gon;Lee, Eung-Don;Cho, Suk-Hee;Choi, Jin-Soo
    • Journal of Broadcast Engineering
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    • v.15 no.2
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    • pp.205-216
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    • 2010
  • In this paper, a method of MPEG-2 Transport Stream (TS) multiplexing for Ultra HDTV (UHDTV) and its design and implementation as a SW tool is described. In practice, UHD video may be divided into several HD videos and each video is encoded in parallel. Therefore, it is necessary to synchronize and multiplex multiple bitstreams encoding each HD video for transmitting and storing UHD video. In this paper, it is assumed that 4 HD videos partitioning a UHD spatially are encoded as H.264/AVC and two 5.0 channel audios are encoded by AC-3. Therefore, 4 H.264/AVC elementary streams (ESs) and 2 AC-3 ESs is mainly considered in the TS multiplexing of UHD. For the carriage of H.264/AVC and AC-3 over MPEG-2 TS, PES packetization and TS multiplexing are designed and implemented based on the extended specification of the MPEG-2 Systems and ATSC (Digital audio compressed standard), respectively. The implemented UHD TS multiplexing tool emulates real time HW operation in the time unit corresponding to the duration of one TS packet transmission in a given TS rate. In particular, in order to satisfy the timing model, the buffers defined in the TS System Target Decoder (T-STD) are monitored and their statuses are considered in the scheduling of TS multiplexing. For UHD multiplexing, two kinds of multiplexing structures, which are UHD re-multiplexing and UHD program multiplexing, are implemented and their strength and weakness are investigated. The developed UHD TS multiplexing tool is tested and verified in terms of the syntax and semantics conformance and functionalities by using a commercial analyzer and real-time presentation tools.

Design and Implementation of a Low-Complexity and High-Throughput MIMO Symbol Detector Supporting up to 256 QAM (256 QAM까지 지원 가능한 저 복잡도 고 성능의 MIMO 심볼 검파기의 설계 및 구현)

  • Lee, Gwang-Ho;Kim, Tae-Hwan
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.6
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    • pp.34-42
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    • 2014
  • This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

Implementation of a Cluster VOD Server and an Embedded Client based on Linux (리눅스 기반의 클러스터 VOD서버와 내장형에 클라이언트의 구현)

  • Seo Dongmahn;Bang Cheolseok;Lee Joahyoung;Kim Byounggil;Jung Inbum
    • Journal of KIISE:Computing Practices and Letters
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    • v.10 no.6
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    • pp.435-447
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    • 2004
  • For VOD systems, it is important to provide QoS to more users under the limited resources. To analyze QoS issues in real environment, we implement clustered VOD server and embedded client system based on the Linux open source platform. The parallel processing of MPEG data, load balancing for nodes and VCR like functions are implemented in the server side. To provide more user friendly interface, the general TV is used for a VOD client's terminal and the embedded board is used supporting for VCR functions. In this paper, we measure the performance of the implemented VOD system under the various user requirement features and evaluate the sources of performance limitations. From these analyses, we propose the dynamic admission control method based on the availability memory and network bandwidth. The proposed method enhances the utilization of the system resource for the more QoS media streams.

A Study on Motion Estimation Encoder Supporting Variable Block Size for H.264/AVC (H.264/AVC용 가변 블록 크기를 지원하는 움직임 추정 부호기의 연구)

  • Kim, Won-Sam;Sohn, Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.10
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    • pp.1845-1852
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    • 2008
  • The key elements of inter prediction are motion estimation(ME) and motion compensation(MC). Motion estimation is to find the optimum motion vectors, not only by using a distance criteria like the SAD, but also by taking into account the resulting number of 비트s in the 비트 stream. Motion compensation is compensate for movement of blocks of current frame. Inter-prediction Encoding is always the main bottleneck in high-quality streaming applications. Therefore, in real-time streaming applications, dedicated hardware for executing Inter-prediction is required. In this paper, we studied a motion estimator(ME) for H.264/AVC. The designed motion estimator is based on 2-D systolic array and it connects processing elements for fast SAD(Sum of Absolute Difference) calculation in parallel. By providing different path for the upper and lower lesion of each reference data and adjusting the input sequence, consecutive calculation for motion estimation is executed without pipeline stall. With data reuse technique, it reduces memory access, and there is no extra delay for finding optimal partitions and motion vectors. The motion estimator supports variable-block size and takes 328 cycles for macro-block calculation. The proposed architecture is local memory-free different from paper [6] using local memory. This motion estimation encoder can be applicable to real-time video processing.