• Journal of the Korea Society of Computer and Information
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• v.16 no.11
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• pp.67-76
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• 2011

This paper describes the development of interactive visualization techniques and a program that allow us to visualize the structure of the volume data and interactively select and visualize the isosurface components using contour tree. The main characteristic of this technique is to provide an algorithm that draws the contour tree in 2D plane in a way that users easily understand the tree, and to provide an algorithm that can efficiently extract an isosurface component utilizing GPU's parallel architecture. The main characteristic of the program we developed through implementing the algorithms is to provide us with an interactive user interface based on the contour tree for extracting an isosurface component and visualization that integrates with previous isosurface and volume rendering techniques. To show the excelland vof our methods, we applied 3D biomedical volume data to our algorithms. The results show that we could interactively select the isosurface components that represent a polypeptide chain, a ventricle and a femur respectively using the user interface based on our contour tree layout method, and extract the isosurface components with 3x-4x higher speed compared to previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Journal of KIISE:Software and Applications
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• v.31 no.5
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• pp.677-696
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• 2004

Component-based software engineering (CBSE) composes reusable components and develops applications with the components. CBSE is admitted to be a new paradigm that reduces the costs and times to develop software systems. The high quality of component designs can be assured if the consistency and correctness among the elements of a component are verified with formal specifications. Current formal languages for components include only some parts of contracts between interfaces, structural aspects and behavioral aspects of component, component-based system, component composition and variability. Therefore, it is not adequate to use current formal languages in all steps of a component design process. In this paper, we suggest a formal language to specify component designs Component-Z. Component-Z extends Object-Z, adds new notations to specify components. It can be possible to specify interfaces, the inner structure of a component, inner workflows, and workflows among interfaces with Component-Z. In addition, Component-Z provides the notations and semantics to specify variability with variation points, variants and required interfaces. The relation between interfaces and components is defined with mapping schemas. Parallel operator is used to specify component composition. It can be possible to describe deployed components with the specifications of component-based systems. Therefore, the formal specification language proposed in this paper can represent all elements to design components. In the case study, we specify an account management system in a bank so that we show that Component-Z can be used in all steps of component design.

• The Korean Journal of Pesticide Science
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• v.9 no.4
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• pp.374-379
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• 2005

Sublethal dose effect of imidacloprid on green peach aphid (Myzus persicae) was investigated. Nymphs of green peach aphid newly produced were counted on 4 days after sub-lethal dose treatment of imidacloprid. Numbers of nymph were not significantly different between $LC_1$ treatment and untreated control. Their numbers of nymph were 8.8 and 12.7 at $LC_1$ and untreated control, respectively. When they were tented at $LC_{10}$, $LC_{30}$ and $LC_{50}$. their numbers of newly produced nymph were 6.0, 5.1 and 3.9 and reduction rates were 52.7%, 59.8% and 69.3% at each treatment compare to untreated control. Reduction rates of newly laid nymph were proportional to the concentrations of imidacloprid treated. Repellent effect of aphid to imidacloprid was bigger in dipping than in watering method. Secretion amount had negative correlation with imidacloprid concentration in dipping method and suppression of secretion went up to 96%. In watering method, amount of secretion did not show any difference between insecticide concentration, but suppression, compared to untreated control, was over 97%.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2006.06a
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• pp.495-505
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• 2006

IT기술기반 교육시스템은 인터넷 등장 이전에도 가능성을 인정받아 지속적으로 개발되어 온 분야이며, 교육공학과의 연계로 지식 전날의 이론체계로 각광을 받고 있다. 사이버교유도 인터넷이전부터 다양한 통신방법을 응용하여 개발되었고, 최근 인터넷을 통하여 사이버 교육시스템은 완벽한 기술기반을 갖추게 되였다. 그러나 IT기술의 급격한 변화로 사이버교육시스템은 계속하여 신기술 변화에 적용해야만 한다. 현재 정보통신기술의 변화는 방송 통신망의 융합, 브로드 밴드 네트워킹, 스마트 디바이스의 다양화, 멀티미디어 기술의 고도화로 요약된다. 이 기술의 종합한 작용으로 유비쿼터스 사회의 기반으로 진화되고 있다. 그래서 e-Learning 분야도 기존 인터넷기반 시스템과는 달리 차세대 온라인교육시스템으로 친화되고 있다. IT융합가술 기반의 온라인 교육시스템은 각종 국제표준단체에서 표준안이 제시되고 있다. e-Learning 시스템이란 선기술 기반을 반영한 표준기술을 사용하는 온라인교육시스템을 포괄하는 개념이다. 본 연구에서는 e-Learning 시스템과 유비쿼터스 기술을 반영한 e-Learning을 비교하였다. 그리고 u-Learning 시스템의 기술정립과 EOD(Education On Demand) 시스템에 대하여 연구하였다. 1. u-Learning 정의 정보산업분야를 비롯한 문화, 교육 등 모든 분야에서 유비퀴터스라는 수식어가 붙어 다니고 있다. e- Learning 교육 업계에 따르면 10년 후에는 유비쿼터스는 대중화가 될 것이며, 부가가치 규모는 100조 원에 이를 것으로 추정된다. 그래서 교육산업도 주변 환경이 아날로그 방식에서 IT 기반에 의한 디지털 환경으로 변화되고 있다. 또한 e러닝, T러닝, m러닝, u러닝 등의 용어가 생성되고 있다.키지에어컨에서 사용되고 있는 밀폐형 압축기에 대해서 그림 2에서 나타내고 있는 냉방능력 10tons(120,000Btu/h) 이하를 중심으로 상기의 최근 기술 동향을 간략하게 소개하고자 한다.질표준의 지표성분으로 간주되는 진세노사이드의 절대함량과 그 성분조성 차이에 따른 임상효과의 차별성이 있는지에 대한 검토와, 특히 최근 실험적으로 밝혀지고 있는 사포닌 성분의 장내 세균에 의한 생물전환체의 인체 실험을 통한 효과 검정이 필요하다. 나아가서는 적정 복용량의 설정과 이와 관련되는 생체내 동태 및 생체이용율(bioavilability)에 관한 정보가 거의 없으므로 이것도 금후 검토해야 할 과제로 사료된다. 인삼은 전통약물로서 오랜 역사성과 그동안의 연구결과에 의한 과학성을 가지고 있으므로 건강유지와 병의 예방 및 회복촉진을 위한 보조요법제 또는 기능성 식품으로써의 유용성이 있는 것으로 판단된다. 앞으로 인삼의 활용성 증대를 위해서는 보다 과학적인 임상평가에 의한 안전성 및 유효성 입증과 제품의 엄격한 품질관리의 필요성이 더욱 강조되어야 할 것이다.xyl radical 생성 억제 효과를 보여 주었다. 본 실험을 통하여 BHT 를 제외하고 전반적으로 세포 수준에서의 oxidative stress 에 대한 억제 효과를 확인해 볼 수 있었으며 특히 수용성 항산화제들에서 두드러진 효과를 보여 주었다. 제공하여 내수기반 확충에도 노력해야 할 것 이다.있었다., 인삼이 성장될 때 부분적인 영양상태의 불충분이나 기후 등에 따른 영향을 받을 수 있기 때문에 앞으로 이에 대한 많은 연구가 이루어져야할 것으로 판단된다.태에도 불구하고 [-wh]의미의 겹의문사는 병렬적 관계의 합성어가 아니라 내부구조를 지니지 않은 단순한 단어(minimal $X^{0}$<

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.66-76
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• 2009

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

• Journal of Convergence for Information Technology
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• v.7 no.2
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• pp.43-51
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• 2017

Background/Objectives : The purpose of this study is to propose a multi-threaded web crawl using queues that can solve the problem of time delay of single processing method, cost increase of parallel processing method, and waste of manpower by utilizing multiple bots connected by wide area network Design and implement. Methods/Statistical analysis : This study designs and analyzes applications that run on independent systems based on multi-threaded system configuration using queues. Findings : We propose a multi-threaded web crawler design using queues. In addition, the throughput of web documents can be analyzed by dividing by client and thread according to the formula, and the efficiency and the number of optimal clients can be confirmed by checking efficiency of each thread. The proposed system is based on distributed processing. Clients in each independent environment provide fast and reliable web documents using queues and threads. Application/Improvements : There is a need for a system that quickly and efficiently navigates and collects various web sites by applying queues and multiple threads to a general purpose web crawler, rather than a web crawler design that targets a particular site.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.5
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• pp.179-187
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• 2003

Recently efficient implementation of finite field operation has received a lot of attention. Among the GF($2^m$) arithmetic operations, multiplication process is the most basic and a critical operation that determines speed-up hardware. We propose a hardware architecture using Mastrovito method to reduce processing time. Existing Mastrovito multipliers using the special generating trinomial p($\chi$)=$x^m$+$x^n$+1 require $m^2$-1 XOR gates and $m^2$ AND gates. The proposed multiplier needs $m^2$ AND gates and $m^2$＋($n^2$-3n)/2 XOR gates that depend on the intermediate term xn. Time complexity of existing multipliers is $T_A$+( (m-2)/(m-n) +1+ log$_2$(m) ) $T_X$ and that of proposed method is $T_X$＋(1＋ log$_2$(m-1)＋ n/2 ) )$T_X$. The proposed architecture is efficient for the extension degree m suggested as standards: SEC2, ANSI X9.63. In average, XOR space complexity is increased to 1.18% but time complexity is reduced 9.036%.

• Korean Journal of Agricultural and Forest Meteorology
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• v.23 no.2
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• pp.122-133
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• 2021

Cultivar parameter calibration can be affected by the reliability of the input data to a crop growth model. In South Korea, two sets of weather stations, which are included in the automated synoptic observing system (ASOS) or the automatic weather system (AWS), are available for preparation of the weather input data. The objectives of this study were to estimate the cultivar parameter using those sets of weather data and to compare the uncertainty of these parameters. The cultivar parameters of CERES-Rice model for Shindongjin cultivar was calibrated using the weather data measured at the weather stations included in either ASO S or AWS. The observation data of crop growth and management at the experiment farms were retrieved from the report of new cultivar development and research published by Rural Development Administration. The weather stations were chosen to be the nearest neighbor to the experiment farms where crop data were collected. The Generalized Likelihood Uncertainty Estimation (GLUE) method was used to calibrate the cultivar parameters for 100 times, which resulted in the distribution of parameter values. O n average, the errors of the heading date decreased by one day when the weather input data were obtained from the weather stations included in AWS compared with ASO S. In particular, reduction of the estimation error was observed even when the distance between the experiment farm and the ASOS stations was about 15 km. These results suggest that the use of the AWS stations would improve the reliability and applicability of the crop growth models for decision support as well as parameter calibration.