• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.217-219
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• 2018

The method on reconfiguring job priority in service queue has been developed to provide seamless service and to enhance operability of Data Service Platform(DSP) in Korean e-Navigation project that performed by Ministry of Oceans and Fisheries(MOF) since 2016. It plays a critical role for providing seamless services of DSP to expect which services ships request to DSP and how much time it costs to make services for responding them to ships in advance. Therefore, as developing a method on reconfiguring jobs in service queue of DSP with a noble algorithm to analyse priority index in parallel, DSP can provide seamless services to ships regardless of data volume and the number of requests that stacked in service queue.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1407-1417
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• 1996

In recent researches on thread partitioning algorithms break a thread at the long latency operation and merge threads to get the longer threads under the given constraints. Due to this limitation, even a program with little parallelism is partitioned into small-sized threads and context-swithings occur frequently. In the paper, we propose another method array localization about the array name, dependence distance(the difference of accessed element index from loop index), and the element usage that indicates whether element is used or defined. Using this information we can allocate array elements to the node where the corresponding loop activation is executed. By array localization, remote accesses to array elements can be replaced with local accesses to localized array elements. As a resuit,the boundaries of some threads are removed, programs can be partitioned into the larger threads and the number of context switchings reduced.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.218-225
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• 2010

This paper deals with a method to minimize the welding time for an AC spot welding system. The spot welding system using a conventional SCR type circuit has a disadvantage of slow control speed and no precise current control. Therefore, recently, the using of inverter type welding system is increasing. Conventional welding machine adopts several tens of switching devices connected in parallel to obtain a huge current of several thousands ampere with a short welding time. This paper analyzed a welding system consisting with 4 IGBT switches for a full-bridge inverter and conventional 60 [Hz] transformer. The simulation and experimental results show the validity of the proposed method.

• The KIPS Transactions:PartA
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• v.10A no.2
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• pp.123-130
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• 2003

This paper presents a new striped checkpointing scheme for serverless cluster computers, where the local disks are attached to the cluster nodes collectively form a distributed RAID with a single I/O space. Striping enables parallel I/O on the distributed disks and staggering avoids network bottleneck in the distributed RAID. We demonstrate how to reduce the checkpointing overhead and increase the availability by striping and staggering dynamically for communication intensive applications. Linpack HPC Benchamark and MPI programs are applied to these checkpointing schemes for performance evaluation on the 16-nodes cluster system. Benchmark results prove the benefits of the striped checkpointing scheme compare to the existing schemes, and these results are useful to design the efficient checkpointing scheme for fast rollback recovery from any single node failure in a cluster system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4C
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• pp.277-282
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• 2012

In this paper, we present a real-time eye contact system for realistic telepresence using a Kinect depth camera. In order to generate the eye contact image, we capture a pair of color and depth video. Then, the foreground single user is separated from the background. Since the raw depth data includes several types of noises, we perform a joint bilateral filtering method. We apply the discontinuity-adaptive depth filter to the filtered depth map to reduce the disocclusion area. From the color image and the preprocessed depth map, we construct a user mesh model at the virtual viewpoint. The entire system is implemented through GPU-based parallel programming for real-time processing. Experimental results have shown that the proposed eye contact system is efficient in realizing eye contact, providing the realistic telepresence.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.58-70
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• 1990

This paper describes a VLSI implementation of real-time two dimensional DCT processor for the subprimary rate video codec system. The proposed architecture exploits the parallelism and concurrency of the distributes architecture for vector inner product operation of DCT and meets the CCITT performance requirements of video codec for full CSIF 30 frames/sec. It is also shown that this architecture satisfies all the CCITT IDCT accuracy specification by simulating the suggested architecture in bit level. The efficient VLSI disign methodology to design suggested architecture is considered and the module generator oriented design environments are constructed based on SUN 3/150C workstation. Using the constructed design environments. the suggensted architecture have been designed by double metal 2micron CMOS technology. The chip area fo designed 8x8 2-D DA-DCT (Distributed Arithmetic DCT) processor is about 3.9mmx4.8mm.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.8
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• pp.773-779
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• 2011

In order to improve fuel economy and emissions, many studies of HEV have been conducted. However, most of these studies concentrate on parallel or power-split HEVs. Series-type HEVs have some advantages over parallel and power-split HEVs. One is that the engine is operated at high efficiency since the engine and the driveshaft are decoupled. Nevertheless, the optimization of the powertrain system of series HEV has not been specifically addressed. We conduct an optimization of the generation system of a series HEV based on the series HEV bus. The main objectives are to simulate the system and to compare the fuel economies of conventional and optimized generation systems.

• Geophysics and Geophysical Exploration
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• v.19 no.3
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• pp.145-152
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• 2016

We used graphics processing units for an efficient time-domain 3D wave propagation modeling. Since graphics processing units are designed for massively parallel processes, we need to optimize the calculation and memory management to fully exploit graphics processing units. We focused on the memory management and examined the performance of programs with respect to the memory management methods. We also tested the effects of memory transfer on the performance of the program by varying the order of finite difference equation and the size of velocity models. The results show that the memory transfer takes a larger portion of the running time than that of the finite difference calculation in programs transferring whole 3D wavefield.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.282-291
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• 2001

In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.