• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Journal of IKEEE
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• v.24 no.2
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• pp.649-653
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• 2020

GPS is a representative satellite navigation system that provides users with accurate location and time information. GPS L1 C / A is opened for civilian and thus utilized in various fields. When the satellite signal reaches the receiver, signal acquisition unit of the digital signal processing hardware searches and acquires the signal among visible satellites. The signal acquisition unit has different implementation methods depending on the signal searching method, such as serial search acquisition, parallel frequency search, parallel code phase search. In this paper, we compare and analyze the three representative acquisition hardwares using live GPS L1 C/A signals. According to the comparison, the parallel code phase search acquisition outperforms the other methods due to reduction of the number of the searchings and a high resolution.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.1-7
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• 1998

Due to the increase in capacity of auxiliary machinery in power plant, the importance of energy saving has been greatly emphasized. If the speed of fans or pumps is controlled in accordance with the variation of load, large electric energy can be saved. Large capacity inverter, 2MVA GTO inverter, has been developed by operating two of 1MVA unit inverters in parallel. The parallel operation of the unit inverter is accomplished through two output transformers of which the secondary windings are connected in series. The system is composed of one control cubicle, one rectifier cubicle and 2 unit inverter cubicles. This inverter system was applied to the sea water lift pump(SLP) driven by a 6.6KV 1500KW induction motor in Seo-Inchon power plant to save the electric energy. The parallel operation of inverters by 180 degrees apart in switching frequency helps to reduce the harmonic components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.35 no.3
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• pp.187-194
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• 2017

The present study introduces a method to parallelize k-means clustering algorithm for fast unsupervised classification of large satellite imagery. Known as a representative algorithm for unsupervised classification, k-means clustering is usually applied to a preprocessing step before supervised classification, but can show the evident advantages of parallel processing due to its high computational intensity and less human intervention. Parallel processing codes are developed by using multi-threading based on OpenMP. In experiments, a PC of 8 multi-core integrated CPU is involved. A 7 band and 30m resolution image from LANDSAT 8 OLI and a 8 band and 10m resolution image from Sentinel-2A are tested. Parallel processing has shown 6 time faster speed than sequential processing when using 10 classes. To check the consistency of parallel and sequential processing, centers, numbers of classified pixels of classes, classified images are mutually compared, resulting in the same results. The present study is meaningful because it has proved that performance of large satellite processing can be significantly improved by using parallel processing. And it is also revealed that it easy to implement parallel processing by using multi-threading based on OpenMP but it should be carefully designed to control the occurrence of false sharing.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.63-66
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• 2001

본 논문에서는 TI사의 TMS320C6201 DSP를 이용하여 H.263 동영상 부호화기를 실시간 구현하고자 한다. 구현한 부호화기는 QCIF 형식의 영상을 사용하여 ITU-T H.263 권고안의 기본 모드를 따라 주로 C 언어와 intrinsics를 사용하여 구현하였다. 특히, 속도 향상을 위해서 고속 메모리의 사용을 극대화하는데 중점을 두었고, 연산량이 많은 모듈에 대한 최적화와 데이터의 병렬 처리 및 DMA (Direct Memory Access) 전송 등을 고려하여 구현하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.628-630
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• 2003

이벤트 알림 시스템에 대한 연구는 비동기적으로 발생되는 이벤트를 기반으로 실행되는 응용 프로그램을 지원하기 위하여 많은 연구가 이루어져 왔다. 본 논문은 확장성과 효율성을 보장하기 위한 Push 기반 이벤트 알림 서비스를 제시한다. 특히 이벤트 중재자(Broker)를 확장하기 쉽게 구현 하였으며, 병렬적 데이터 전송 등을 통하여 데이터 전송 효율성을 제공해 주고 있다. 또한 XML을 사용한 레코드 기반 이벤트 모델을 구현하여 이기종 호환성 보장과 구현 언어 독립적인 구조를 제공하고 있다. 구현된 이벤트 알림 서비스에 대해 구현 이슈를 살펴보고, 성능 측정하고 그 결과를 분석한다.

• 전기의세계
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• v.49 no.11
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• pp.28-35
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• 2000

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1992.06a
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• pp.396-400
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• 1992