• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1908-1918
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• 2013

Free-view, auto-stereoscopic video service is a next generation broadcasting system which offers a three-dimensional video, images of the various point are needed. This paper proposes a method that parallelizes the algorithm for arbitrary intermediate view-point image fast generation and make it faster using General Propose Graphic Processing Unit(GPGPU) with help of the Compute Unified Device Architecture(CUDA). It uses a parallelized stereo-matching method between the leftmost and the rightmost depth images to obtain disparity information and It use data calculated disparity increment per depth value. The disparity increment is used to find the location in the intermediate view-point image for each depth in the given images. Then, It is eliminate to disocclusions complement each other and remaining holes are filled image using hole-filling method and to get the final intermediate view-point image. The proposed method was implemented and applied to several test sequences. The results revealed that the quality of the generated intermediate view-point image corresponds to 30.47dB of PSNR in average and it takes about 38 frames per second to generate a Full HD intermediate view-point image.

• Journal of Internet Computing and Services
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• v.15 no.2
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• pp.19-31
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• 2014

In this paper, a parallel backoff delay procedure on multiple IEEE 802.15.4 channels and a channel searching method considering the frequency spectrum of WiFi traffic are studied for IEEE 802.15.4 nodes to avoid the interference from WiFi traffic. In order to search the channels being occupied by WiFi traffic, we analyzed the methods measuring the powers of adjacent channels simultaneously, checking the duration of measured power levels greater than a threshold, and finding the same periodicity of sampled RSSI data as the beacon frame by signal processing. In an wireless channel overlapped with IEEE 802.11 network, the operation of CSMA-CA algorithm for IEEE 802.15.4 nodes is explained. A method to execute a parallel backoff procedure on multiples IEEE 802.15.4 channels by an IEEE 802.15.4 device is proposed with the description of its algorithm. When we analyze the data measured by the experimental system implemented with the proposed method, it is observed that medium access delay times increase at the same time in the associated IEEE 802.15.4 channels that are adjacent each other during the generation of WiFi traffic. A channel evaluation function to decide the interference from other traffic on an IEEE 802.15.4 channel is defined. A channel searching method considering the channel evaluations on the adjacent channels together is proposed in order to search the IEEE 802.15.4 channels interfered by WiFi, and the experimental results show that it correctly finds the channels interfered by WiFi traffic.

• The Journal of the Korea Contents Association
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• v.9 no.5
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• pp.13-23
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• 2009

One of the main purpose of multiple-view image processing technology is support realistic 3D image to device user by using multiple viewpoint display devices and compressed data restoration devices. This paper proposes a multiple view image synthesis scheme based on RAM disk which makes possible to browse 3D images generated by applying effective composing method to real time input stereo images. The proposed scheme first converts input images to binary image. We applies edge detection algorithm such as Sobel algorithm and Prewiit algorithm to find edges used to evaluate disparities from images of 4 multi-cameras. In addition, we make use of time interval between hardware trigger and software trigger to solve the synchronization problem which has stated ambiguously in related studies. We use a unique identifier on each snapshot of images for distributed environment. With respect of performance results, the proposed scheme takes 0.67 sec in each binary array. to transfer entire images which contains left and right side with disparity information for high quality 3D image browsing. We conclude that the proposed scheme is suitable for real time 3D applications.

• Journal of KIISE
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• v.42 no.4
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• pp.530-540
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• 2015

Industrial WSNs need great performance and reliable communication. In industrial WSNs, cluster structure reduces the cost to form a network, and the reservation-based MAC is a more powerful and reliable protocol than the contention-based MAC. Depth-based TDMA assigns time slots to each sensor node in a cluster-based network and it works in a distributed manner. DB-TDMA is a type of depth-based TDMA and guarantees scalability and energy efficiency. However, it cannot allocate time slots in parallel and cannot perfectly avoid a collision because each node does not know the total network information. In this paper, we suggest an improved distributed algorithm to reduce the end-to-end delay of DB-TDMA, and the proposed algorithm is compared with DRAND and DB-TDMA.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1441-1446
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• 2014

For the escape from a maze, the cooperative method by robot swarm was proposed in this paper. The robots can freely move by collecting essential data and making a decision in the use of sensors; however, a central control system is required to organize all robots for the escape from the maze. The robots explore new mazes and then send the information to the system for analyzing and mapping the escaping route. Three issues were considered as follows for the effective escape by multiple robots from the mazes in this paper. In the first, the mazes began to divide and secondly, dead-ends should be blocked. Finally, after the first arrivals at the destination, a shortcut should be provided for rapid escaping from the maze. The parallel-escape algorithms were applied to the different size of mazes, so that robot swarm can effectively get away the mazes.

• Journal of KIISE:Software and Applications
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• v.31 no.4
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• pp.387-393
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• 2004

DNA computing is technology that applies immense parallel castle of living body molecules into information processing technology, and has used to solve NP-complete problems. However, there are problems which do not look for solutions and take much time when only DNA computing technology solves NP-complete problems. In this paper we proposed an algorithm called ACO(Algorithm for Code Optimization) that can efficiently express DNA sequence and create good codes through composition and separation processes as many as the numbers of reaction by DNA coding method. Also, we applied ACO to Hamiltonian path problem of NP-complete problems. As a result, ACO could express DNA codes of variable lengths more efficiently than Adleman's DNA computing algorithm could. In addition, compared to Adleman's DNA computing algorithm, ACO could reduce search time and biological error rate by 50% and could search for accurate paths in a short time.

• Journal of Broadcast Engineering
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• v.26 no.2
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• pp.167-174
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• 2021

Recently, deep learning technology is widely used in various computer vision applications, such as object recognition, classification, and image generation. In particular, the deep learning-based super-resolution has been gaining significant performance improvement. Fast super-resolution convolutional neural network (FSRCNN) is a well-known model as a deep learning-based super-resolution algorithm that output image is generated by a deconvolutional layer. In this paper, we propose an FPGA-based convolutional neural networks accelerator that considers parallel computing efficiency. In addition, the proposed method proposes Optimal-FSRCNN, which is modified the structure of FSRCNN. The number of multipliers is compressed by 3.47 times compared to FSRCNN. Moreover, PSNR has similar performance to FSRCNN. We developed a real-time image processing technology that implements on FPGA.

• The Journal of the Convergence on Culture Technology
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• v.4 no.4
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• pp.373-377
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• 2018

In this paper, we propose an implementation of a neural network accelerator for reducing the rendering noise using OpenCL. Among the rendering algorithms, we selects a ray tracing to assure a high quality graphics. Ray tracing rendering uses ray to render, less use of the ray will result in noise. Ray used more will produce a higher quality image but will take operation time longer. To reduce operation time whiles using fewer rays, Learning Base Filtering algorithm using neural network was applied. it's not always produce optimize result. In this paper, a new approach to Matrix Multiplication that is based on General Matrix Multiplication for improved performance. The development environment, we used specialized in high speed parallel processing of OpenCL. The proposed architecture was verified using Kintex UltraScale XKU6909T-2FDFG1157C FPGA board. The time it takes to calculate the parameters is about 1.12 times fast than that of Verilog-HDL structure.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.20 no.1
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• pp.3-16
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• 2010

Recently in the field of the wireless sensor network, many researchers are attracted to pairing cryptography since it has ability to distribute keys without additive communication. In this paper, we propose efficient hardware implementation of ${\eta}_T$ pairing which is one of various pairing scheme. we suggest efficient hardware architecture of ${\eta}_T$ pairing based on parallel processing and register/resource optimization, and then we present the result of our FPGA implementation over GF($2^{239}$). Our implementation gives 15% better result than others in Area Time Product.