• Journal of Broadcast Engineering
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• v.6 no.2
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• pp.169-176
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• 2001

Most of the previous video watermarking algorithms cannot be supported by real-time video processing. The maul reason is that in order to develop a robust algorithm the watermarking technique requires a very high computational cost when embedding and extracting the watermark in various frequency domains. Previous embedding methods simultaneously try to compress a video by MPEG and embed a watermark supporting real-time processing. However, In this paper, our proposed algorithm can support real-time processing in both spatial and frequency domains. First. the watermark is created on the courier transform domain, and next is inverse-Fourier-transformed ; then, we directly embed it into the video frame In the spatial domain. This procedure does not require a lot of the computational cost during embedding because of the spatial domain processing. Also, it is possible to support a video stream service and a very robust algorithm from MPEG compression and various geometric attacks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.386-392
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• 2015

Data in a image compression codec are processed with a specific regular block size. The processing order of block sized data is changed in specific function blocks and the data is packed in memory and read by a new sequence. To maintain a regular throughput rate, double buffering is normally used that interleaving two block sized memory to do concurrent read and write operations. Single buffering using only one block sized memory can be adopted to the simple data reordering, but when a complicate reordering occurs, irregular address changes prohibit from implementing adequate address generating for single buffering. This paper shows that there is a predictable and recurring regularity of changing address access orders within a finite updating counts and suggests an effective method to implement. The data reordering function using suggested idea is designed with HDL and implemented with TSMC 0.18 CMOS process library. In various scan blocks, it shows more than 40% size reduction compared with a conventional method.

• KIISE Transactions on Computing Practices
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• v.22 no.3
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• pp.127-132
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• 2016

Several methods have been proposed to apply artificial neural networks to text compression in the past. However, the networks and targets are both limited to the small size due to hardware capability in the past. Modern GPUs have much better calculation capability than CPUs in an order of magnitude now, even though CPUs have become faster. It becomes possible now to train greater and complex neural networks in a shorter time. This paper proposed a method to transform the distribution of original data with a probabilistic neural predictor. Experiments were performed on a feedforward neural network and a recurrent neural network with gated-recurrent units. The recurrent neural network model outperformed feedforward network in compression rate and prediction accuracy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.9
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• pp.765-774
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• 2013

In this paper, we present a cooperative compressed spectrum sensing scheme for correlated signals in decentralized wideband cognitive radio networks. Compressed sensing is a signal processing technique that can recover signals which are sampled below the Nyquist rate with high probability, and can solve the necessity of high-speed analog-to-digital converter problem for wideband spectrum sensing. In compressed sensing, one of the main issues is to design recovery algorithms which accurately recover original signals from compressed signals. In this paper, in order to achieve high recovery performance, we consider the multiple measurement vector model which has a sequence of compressed signals, and propose a cooperative sparse Bayesian recovery algorithm which models the temporal correlation of the input signals.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.37-48
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• 2005

The efficiency of power supply circuits such as DC-DC converters and batteries varies on the trend of the power consumption because their efficiencies are not fixed. To analyze the efficiency of power supply circuits, we need the temporal behavior of the power consumption of the loads, which is dependent on the activity factors of the devices during the operation. Since it is not easy to model every detail of those factors, one of the most accurate power consumption analyses of power supply circuits is measurement of a real system, which is expensive and time consuming. In this paper, we introduce an active load emulator for embedded systems which is capable of power measurement, logging, replaying and synthesis. We adopt a pattern recognition technique for data compression in that long-term behaviors of power consumption consist of numbers of repetitions of short-term behaviors, and the number of short-term behaviors is generally limited to a small number. We also devise a heterogeneous structure of active load elements so that low-speed, high-current active load elements and high-speed, low-current active load elements may emulate large amount and fast changing power consumption of digital systems. For the performance evaluation of our load emulator, we demonstrate power measurement and emulation of a hard drive. As an application of our load emulator, it is used for the analysis of a DC-DC converter efficiency and for the verification of a low-power frequency scaling policy for a real-time task.

• Journal of Broadcast Engineering
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• v.26 no.2
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• pp.167-174
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• 2021

Recently, deep learning technology is widely used in various computer vision applications, such as object recognition, classification, and image generation. In particular, the deep learning-based super-resolution has been gaining significant performance improvement. Fast super-resolution convolutional neural network (FSRCNN) is a well-known model as a deep learning-based super-resolution algorithm that output image is generated by a deconvolutional layer. In this paper, we propose an FPGA-based convolutional neural networks accelerator that considers parallel computing efficiency. In addition, the proposed method proposes Optimal-FSRCNN, which is modified the structure of FSRCNN. The number of multipliers is compressed by 3.47 times compared to FSRCNN. Moreover, PSNR has similar performance to FSRCNN. We developed a real-time image processing technology that implements on FPGA.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.3
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• pp.42-48
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• 2002

Multiple description coding Is source coding for multiple channels such that a decoder which receives an arbitrary subset of the channels may produce a useful reconstruction. This paper presents an efficient multiple description coder using a newly designed EZW coding method. We first propose EZW coder which has expanded threshold and two subordinate passes. And then we present multiple description coder which has two coding channels using the proposed EZW coders. To evaluate the performance of the proposed coder, we provide an image coding applications with two descriptions and compare multiple description image coding results reported to date. Simulation results show that the proposed method has a better performance than the polyphase transform method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.398-407
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• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.1-7
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• 1999

We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.194-203
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• 1998

In this paper, a new DCT-VQ method is proposed which can solve the problems of VQ such as the degradation of edge and enormous calculations. VQ is carried in DCT domain but spatial domain in order to protect the degradation of edge. DCT makes high correlated image data decorrelated and the energy concentrated on a few coefficients. In DCT domain, the DC coefficient is quantized with 8 bits uniform scalar quantizer and the AC coefficients are divided to three regions and coded with vector qiantizer for considering edge components. For the decrease of the calculation and memory, the vectors for three region have small dimension of $1{\times}7$ and use the same codebook. Thus, the proposed method can fully express the edge components by considering AC coefficients in DCT domain and decrease the calculation and memory be reducing the dimension of vectors.