• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.63-71
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• 2000

A new type of second-order digital peaking filters for professional-quality digital audio system is proposed whose frequency response can be elaborately controlled throughout the composite structure of a standard band-pass filter and a 0-dB bypass gain. The proposed method for designing the peaking filter uses the Q-compensation technique to prevent the Q-distortion caused by the variation of the gain factor and is reduced into a compact form which is proper to the real-time implementation. Methods are examined for computing its coefficients, which are exact and very straightforward to compute with small amount of the system resources.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.36 no.7
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• pp.674-679
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• 2008

In this paper, we introduce a new design approach for self-sustained resonant accelerometer, that takes advantage of the automatic gain control (AGC) loop to achieve a stabilized oscillation dynamics. Fundamental idea of this accelerometer is to maintain uniform amplitude of oscillation under input accelerations. Through system modeling and loop transformation considering the envelope of oscillation, the controller is designed to maintain uniform amplitude in oscillation under dynamic input acceleration. The simulation results demonstrate the feasibility of the proposed accelerometer design, which is applicable to control grade inertial measurement system in industrial and civil application fields.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.35-43
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• 2013

As texture images have become prevalent throughout a variety of industrial applications, copyright protection of these images has become important issues. For this reason, this paper proposes a color-texture image watermarking algorithm utilizing texture properties inherent in the image. The proposed algorithm selects suitable blocks to embed a watermark using the energy and homogeneity properties of the grey level co-occurrence matrices as inputs for the fuzzy c-means clustering algorithm. To embed the watermark, we first perform a discrete wavelet transform (DWT) on the selected blocks and choose one of DWT subbands. Then, we embed the watermark into discrete cosine transformed blocks with a gain factor. In this study, we also explore the effects of the DWT subbands and gain factors with respect to the imperceptibility and robustness against various watermarking attacks. Experimental results show that the proposed algorithm achieves higher peak signal-to-noise ratio values (47.66 dB to 48.04 dB) and lower M-SVD values (8.84 to 15.6) when we embedded a watermark into the HH band with a gain factor of 42, which means the proposed algorithm is good enough in terms of imperceptibility. In addition, the proposed algorithm guarantees robustness against various image processing attacks, such as noise addition, filtering, cropping, and JPEG compression yielding higher normalized correlation values (0.7193 to 1).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1030-1038
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• 2013

The proposed Alamouti coded OFDM effectively cancels Inter Carrier Interference (ICI) due to frequency offset between distributed antennas. The conventional Alamouti coded OFDM schemes to mitigate ICI utilize N-point Inverse Fast Fourier Transform/Fast Fourier Transform (IFFT/FFT) operations for OFDM modulation and demodulation processes with total N subcarriers. However, the performance degrades because ICI is also repeated in N periods due to the property of N-point IFFT/FFT operation. In order to avoid this problem, null data are used at the subcarriers with large ICI and thus, data rate decreases. The proposed scheme employs 2N-point IFFT/FFT instead of N-point IFFT/FFT in order to increase sampling rate. By increasing sampling rate, the amount of interference significantly decreases because the period of ICI also increases. The proposed scheme increases the data rate and improves the performance by reducing amount of ICI and the number of null-data. Furthermore, the gain of the performance and data rate of the proposed scheme is significant with higher modulation such as 16-Quadarature Amplitude Modulation (QAM) or 64-QAM.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.555-556
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• 2015

MPEG 의 Royalty-Free 비디오 코덱의 하나로 표준화 중인 IVC(Internet Video Coding)에서는 화면내(intra) 예측부호화에서 부호화 이득을 위하여 $4{\times}4$ 블록 예측 및 $4{\times}4$ 블록 변환을 포함하고 있다. 반면, 화면간(inter) 예측부호화에서는 $16{\times}16$ 블록에서 최소 $8{\times}8$ 블록까지의 가변크기 블록에 대한 예측만 가능하다. 보다 복잡한 영상의 경우 보다 작은 블록에 대한 화면간 예측을 통하여 부호화의 성능 개선을 개선할 수 있다. 본 논문에서는 기존의 화면간 예측의 블록 크기를 $4{\times}4$ 블록까지 확장하여 화면간 예측부호화 성능을 개선한다. 실험결과 제안기법은 기존의 ITM 12.0 대비 다양한 테스트 시퀀스의 휘도성분에서 평균적으로 비트율 절감의 이득은 없으나 대부분의 클래스에서 성능개선을 보였고 추가적인 최적화가 필요함을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.5-8
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거 하기 위해서, 베이스 부분의 매몰충을 줄여서 npn트랜지스터의 베이스와 에피충과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 소자 시뮬레이션의 자료를 얻기 위하여 수직 npn 트랜지스터와 병합 pnp 트랜지스터의 전류-전압 특성을 분석하여 특성 파라미터를 추출하였다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 형성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.151-154
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거하기 위해서, 베이스 부분의 매몰층을 줄여서 npn트랜지스터의 베이스와 에피층과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 헝성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.4
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• pp.195-202
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• 2002

The high performance position controller named 'Unified PID Position Controller'is presented in part 1 of this paper. In part 2, we provide smart gain adjustment methods including the freedom utilizations for rare sensitivity toward the system parameter variation and for increasing the stiffness of the system. Owing to the provided gain tuning strategy, the overall system characteristics can be stabilized without over-shoot phenomena when the system parameter is changed in the rate of from 0.5 to 2∼4. Moreover, for the actual feasibility to the industrial fields, a simple butt effective anti-windup strategy prohibiting the integral component of the PID position controller from saturation is presented too. All of the presented algorithms are verified through the experiment works with commercial linear motor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.430-434
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• 2002

Recently, lot of researchers pay attention to custom power equipments for power quality improvement, especially, voltage stabilization equipment using PWM AC-AC converter. In this paper, voltage regulation system with PWM Buck-Boost AC-AC converter is proposed and then the system is modelled and analyzed by using of Circuit DQ transformation whereby steady state characteristics such as equations for voltage gain and power factor are obtained. The equations become guide line for system design by showing the effect on system operations. Finally, some experiment will show validity of analysis.