• Journal of Advanced Navigation Technology
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• v.27 no.5
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• pp.587-593
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• 2023

In this paper, we propose a systematic design approach based on cavity-mode resonance analysis to improve the radiated susceptibility of cables in air vehicles. As electronic devices equipped in air vehicles substantially increase, enhancing the radiated susceptibility of internal cables becomes more challenging and significant. The proposed design approach provides an efficient method to avoid and suppress cavity-mode resonances using analytical methods to estimate the resonance frequencies and the current ratio induced by the cavity-mode resonances. It is demonstrated in simulated results that the proposed method offers a design solution for improving the radiated susceptibility and reduces the computation time by up to 99.6% compared to the previous design method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.64-74
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• 1999

A new clock skew optimization for clock routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevent the total wire length from increasing. As the clock skew is the major constraint for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization can increase total wire length, therefore clock routing is performed within the given skew bound which can not induce the malfunction. Clock routing under the specified skew bound can decrease total wire length Not only total wire length and delay time minimization algorithm using merging point relocation method but also clock skew reduction algorithm using link-edge insertion technique between two nodes whose delay difference is large is proposed. The proposed algorithm construct a new clock routing topology which is generalized graph model while previous methods uses only tree-structured routing topology. A new cost function is designed in order to select two nodes which constitute link-edge. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance difference is short. Furthermore, routing topology construction and wire sizing algorithm is developed to reduce clock delay. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the delay reduction under the given skew bound.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.89-101
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• 2006

Frequency-variant transmission line parameters are determined. Then the signal transient characterizations of frequency-dependent multi-coupled lines are investigated. With the proposed method, an accurate signal integrity degradation such as signal ringing (overshoot, undershoot) and crosstalk noises relevant to the switching patterns of signals, rising / falling time(tr, tf) and line lengths is investigated. It is shown that there may be approximately 26% discrepancy of signal transients and 260% difference of crosstalk noises between the constant RLC model and frequency-variant RLC model in on-chip global interconnects while those of package lines are 11% and 70%, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.4
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• pp.431-435
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• 2008

Since previous work CDP(Congestion Driven Placement) [1] considers all possible directions to move every cell in nets which contribute highly to routing congestion, it consumes CPU time a lot. In this paper, we propose a faster global placement technique, so called ICDGP(Improved Congestion Driven Global Placement) to relieve the routing congestion. ICDGP uses the force-directed method to determine the target locations of the cells in the nets in the congested spots, and considers only to move the target location for each cell. If moving multiple cells simultaneously is considered better than moving each cell one by one it moves multiple cells simultaneously. By experimental results, ICDGP produces less congested placement than CDP does. Particularly, the CPU time is reduced by 36% on average.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.121-121
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• 2000

반도체 산업의 발달에 따라 소자의 보다 빠른 동작 속도와 큰 집적도를 갖은 ULSI 구조를 얻기 위해, 새로운 금속배선 재료가 요구되고 있다. 기존의 금속 배선인 Al 및 Al 합금은 비교적 낮은 비저항과 박막형성의 용이함으로 인하여 현재까지 금속배선 재료로 사용되고 있으나, 고집적화에 따라 RC Time Delay와 Electromigration의 문제점을 들어내었다. 이러한 문제를 해결할 새로운 배선 재료로 Al보다 낮은 비저항을 가지며, electromigration 저항성을 갖는 Cu 금속배선 재료가 활발히 연구되고 있다. 본 실험에서는 (100) Si 웨이퍼를 기판으로 사용하였으며, 각층은 SiO2/Si3N4/EP Cu/Seed Cu/ TaN/SiO2/Si wafer 상태로 증착하였다. 확산방지막으로 TaN을 사용하였고, seed Cu는 sputtering 으로 증착하였으며, seed Cu 만으로 된 박막과 seed Cu + electro plating Cu로 구성된 박막을 제작하였다. 제작 완료된 박막은 N2 분위기에서 20$0^{\circ}C$ 120 min, 45$0^{\circ}C$ 60min 동안 열처리하여 Cu 박막의 조직 변화를 TEM 및 여러 분석방법을 이용하여 분석하였다. Plan-view TEM결과, 45$0^{\circ}C$, 60min 열처리함에 따라 결정립 성장이 일어난 것을 확인 할 수 있었다. 그러나, 성장후에도 twin boundary, stacking fault, dislocation, small defect 등은 여전히 남아 있음이 관찰된다. 그림 1(a)는 as-deposit 상태이며, 그림 1(b)는 45$0^{\circ}C$, 60min 열처리한 plan-view TEM 사진이다.

• Journal of the Korean Vacuum Society
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• v.8 no.1
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• pp.31-35
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• 1999

In this paper, the lifetime dependence as a function of the line length of Al-1%Si thin film interconnections due to electromigration in semiconductor devices was studied. Al-1%Si thin film interconnections with a pattern of straight type were formed by using a standard photolithography process. The test patterns manufactured have line lengths in the range of 100 to 1600 $mu extrm{m}$. Al-1%Si thin film interconnections with Ti underlayers showed longer lifetime than those without Ti underlayers. Ti underlayers are believed to improve electromigration resistance resulting in a longer lifetime in Al-1%Si thin film interconnections. The dependence of lifetime on the line length in Al-1%Si/Ti thin film interconnections shows a saturation tendency near 800 $\mu\textrm{m}$ line length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.62-72
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• 2003

This paper deals with a crosstalk minimization method by wire spacing. The suggested method uses linear programming method and consider crosstalk of both horizontal segments and vertical segments. In this paper, we suggest a method which can predict the coupling length between vertical segments in the final routing result using longest path algorithm. By the suggested method, we can make LP problem without integer variable. Therefore, it is much faster to solve the problem. In the case of crosstalk optimization, the suggested method optimized peak crosstalk 11.2%, and 3% total crosstalk more than wire perturbation method. The execution time of the suggested method is as fast as it takes 11 seconds when Deutsch is optimized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.252-255
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• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.249-257
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• 1998

다층 인쇄회로기판에서 고속 신호를 정확하고 신속하게 배선 설계하려면, 물리적 설계 규칙과 신호 잡음을 고려한 전기적 설계 규칙을 정립하고, 적용할 신호 검증 도구를 사용하여 신호의 충실성을 검증하여야 한다. 본 논문은 현재 개발 제작되어 동작 중에 있는 HIPSS(High Performance Storage System)보드에 대한 전기적 설계 규칙과 고속 신호의 배선에 따른 일부 고속 신호의 신호 검증 방법을 설명한다. 또한 전기적 설계 규칙을 적용하여 인쇄회로기판을 설계하는 경우, 발생하는 신호 지연, 반사 그리고 누화 등의 신호 잡음을 검증 도구를 이용하여 시뮬레이션 하고, 분석한 결과를 보이며, 수정된 고속 신호의 배선 설계를 확인한다.

• Electronics and Telecommunications Trends
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• v.3 no.1
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• pp.99-109
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• 1988

전자회로의 설계 자동화에 있어 중요한 단계인 레이아웃(layout)의 주기능은 배치(placement)와 배선(routing)이라 할 수 있으며, 그중 배치는 크게 constructive와 iterative의 두 부류로 나누어진다. 이들의 가장 주된 목적은 배치의 다음과정인 배선(routing)에서 높은 배선율(routability)을 이룰 수 있도록 하는 데 있다. 본고에서는 배치에 있어서 일반적으로 사용되는 알고리즘과 개발동향에 대해 살펴봄으로써 앞으로 새로운 알고리즘의 개발과 자동설계 시스팀의 효율적인 사용에 도움이 되도록 하였다.