• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.169-174
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• 2005

In this paper, we proposed a new algorithm of the inverse scattering for the reconstruction of unknown dielectric scatterers using the finite-difference time-domain method and the design sensitivity analysis. We introduced the design sensitivity analysis based on the gradient for the fast convergence of the reconstruction. By introducing the adjoint variable method for the efficient calculation, we derived the adjoint variable equation. As an optimal algorithm we used the steepest descent method and reconstructed the dielectric targets using the iterative estimation. To verify our algorithm we will show the numerical examples for the two-dimensional $TM^2$ cases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.117-123
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• 2007

Catadioptric mirrors are widely used in automatic surveillance system. The major drawback of catadioptric mirror is its unequal image resolution. Equidistance catadioptric mirrir can be the solution to this problem. The exact axial alignment and the exact mount of mirror are the sources that can be avoided but the focal length variation is inevitable. In this paper, the effects of focal length variation on the computation of depth and height of object' point are explained and the effective and simple focal length finding algorithm is presented. First two object's points are selected, and the counterparts on the other stereo image are to be found using MSE criterion. Using four pixel distance from the image center, the assumed focal length is calculated. If the obtained focal length is different from the exact focal length, 24mm, the focal length value is modified by the proposed method. The method is very simple and gives the comparable results with the earlier sophisticated method.

• 전자공학회논문지 IE
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• v.49 no.2
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• pp.18-23
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• 2012

A method to determine the equivalent circuits of broadband ultrasound transducers is necessary for designing filters that match the impedances of the transducer and the analysis of the transducer. A method is proposed to determine the equivalent circuits of broadband transducers with 2 resonances in the frequency band of interest. The circuit parameters are estimated by iterative Levy method with the measured electrical conductance data. The method is illustrated by computing the conductance and susceptance of the equivalent circuits of 3 types of broadband transducers. The equivalent circuit of a transducer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.279-282
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• 2012

In this paper, a hardware architecture of phase calculator for 3D image processing is proposed. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. Phase calculator designed in Verilog HDL is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.430-432
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• 2015

This paper describes a hardware implementation of ultra-lightweight block cipher algorithm PRESENT-80/128 that supports for two master key lengths of 80-bit and 128-bit. The PRESENT algorithm that is based on SPN (substitution and permutation network) consists of 31 round transformations. A round processing block of 64-bit data-path is used to process 31 rounds iteratively, and circuits for encryption and decryption are designed to share hardware resources. The PRESENT-80/128 crypto-processor designed in Verilog-HDL was verified using Virtex5 XC5VSX-95T FPGA and test system. The estimated throughput is about 550 Mbps with 275 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.