• Title/Summary/Keyword: 문턱 값

Search Result 471, Processing Time 0.025 seconds

Scaling theory to minimize the roll-off of threshold voltage for nano scale MOSFET (나노 구조 MOSFET의 문턱전압 변화를 최소화하기 위한 스케일링 이론)

  • 김영동;김재홍;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2002.11a
    • /
    • pp.494-497
    • /
    • 2002
  • In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.

  • PDF

Improvement of Recognition Speed for Real-time Address Speech Recognition (실시간 주소 음성인식을 위한 인식 시스템의 인식속도 개선)

  • Hwang Cheol-Jun;Oh Se-Jin;Kim Bum-Koog;Jung Ho-Youl;Chung Hyun-Yeol
    • Proceedings of the Acoustical Society of Korea Conference
    • /
    • spring
    • /
    • pp.74-77
    • /
    • 1999
  • 본 논문에서는 본 연구실에서 개발한 주소 음성인식 시스템의 인식 속도를 개선시키기 위하예 새로운 가변 프루닝 문턱치를 적용하는 방법을 제안하고 실험을 통하여 그 유효성을 확인하였다. 기존의 가변 프루닝 문턱치는 일정 프레임이 경과하면 일정 값을 가진 문턱치를 계속하여 감소시켜나가는 방법을 반복하기 때문에, 불필요한 탐색공간을 탐색하게 된다. 본 논문에서 새로이 제안하는 가변 프루닝 문턱치를 채용하는 방법은 처음 일정 구간이 경과되면 일정 문턱치를 감소시키나, 다음 일정 프레임에서는 탐색되어야할 후보에 따라서 문턱치를 변화시켜 프루닝시키기 때문에 탐색공간을 효과적으로 감소시킬 수 있다. 제안된 방법의 유효성을 확인하기 위하여, 본 연구실에서 개발한 한국어 주소 입력 시스템에 적용하였다. 이 시스템은 48개의 연속 HMM 유사음소단위(Phoneme Like Units; PLUs)를 인식의 기본단위로 하고, .사용환경 변화에 의한 인식성능의 저하를 최소화하기 위해 최대사후 확률추정법(Maximum A Posteriori Probability Estimation; MAP)을 사용하며, 인식알고리즘으로는OPDP(One Pass Dynamic Programming)법을 이용하고 있다. 남성화자 3인에 의한 75개의 연결주소명을 이용하여 인식 실험을 수행한 결과 고정 프루닝 문턱치를 적용한 경우 인식률은 평균 $96.0\%$, 인식 시간은 5.26초였고, 기존의 가변 프루닝 문턱치의 경우 인식률은 평균 $96.0\%$, 인식 시간은 5.1초인 데 비하여, 새로운 가변 프루닝 문턱치를 적용찬 경우에는 인식률 저하없이 인식 시간이 4.34초로, 기존에 비해 각각 0.92초, 0.76초 인식 시간이 감소되어 제안한 방법의 유효성을 확인할 수 있었다.는 달리 각 산란 영역에서 그 지수는 1씩 작은 값을 갖는다.향에 따라 음장변화가 크게 다를 것이 예상되므로 이를 규명하기 위해서는 궁극적으로 3차원적인 음장분포 연구가 필요하다. 음향센서를 해저면에 매설할 경우 수충의 수온변화와 센서 주변의 수온변화 사이에는 어느 정도의 시간지연이 존재하게 되므로 이에 대한 영향을 규명하는 것도 센서의 성능예측을 위해서 필요하리라 사료된다.가지는 심부 가스의 개발 성공률을 증가시키기 위하여 심부 가스가 존재하는 지역의 지질학적 부존 환경 및 조성상의 특성과 생산시 소요되는 생산비용을 심도에 따라 분석하고 생산에 수반되는 기술적 문제점들을 정리하였으며 마지막으로 향후 요구되는 연구 분야들을 제시하였다. 또한 참고로 현재 심부 가스의 경우 미국이 연구 개발 측면에서 가장 활발한 활동을 전개하고 있으며 그 결과 다수의 신뢰성 있는 자료들을 확보하고 있으므로 본 논문은 USGS와 Gas Research Institute(GRI)에서 제시한 자료에 근거하였다.ऀĀ耀Ā삱?⨀؀Ā Ā?⨀ጀĀ耀Ā?돀ꢘ?⨀硩?⨀ႎ?⨀?⨀넆돐쁖잖⨀쁖잖⨀/ࠐ?⨀焆덐瀆倆Āⶇ퍟ⶇ퍟ĀĀĀĀ磀鲕좗?⨀肤?⨀⁅Ⴅ?⨀쀃잖⨀䣙熸ጁ↏?⨀

  • PDF

Fast Mode Decision Method for HEVC in Depth Video (HEVC를 위한 깊이 영상 고속 모드 결정 방법)

  • Yoon, Da-Hyun;Ho, Yo-Sung
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.37 no.1A
    • /
    • pp.51-56
    • /
    • 2012
  • In order to reduce the complexity of HEVC, we propose a fast mode decision algorithm in depth videos. Since almost CU mode is decided as SKIP mode in depth-continuity regions, we design the algorithm using the property of depth videos. If cost of SKIP is smaller than the multiplication between the threshold for EarlySKIP and average cost of SKIP, EarlySKIP is performed. Otherwise, we calculate Inter $2N{\times}2N$. Then, if motion vector of Inter $2N{\times}2N$ is 0 and variance of CU is smaller than threshold for inter, we skip Inter $2N{\times}N$, Inter $N{\times}2N$. Experimental results show that our proposed algorithm reduces the encoding time from 39% to 82% with negligible PSNR loss and bitrate increase.

Design of the Noise Suppressor Using the Perceptual Model and Wavelet Packet Transform (인지 모델과 웨이블릿 패킷 변환을 이용한 잡음 제거기 설계)

  • Kim, Mi-Seon;Park, Seo-Young;Kim, Young-Ju;Lee, In-Sung
    • The Journal of the Acoustical Society of Korea
    • /
    • v.25 no.7
    • /
    • pp.325-332
    • /
    • 2006
  • In this paper. we Propose the noise suppressor with the Perceptual model and wavelet packet transform. The objective is to enhance speech corrupted colored or non-stationary noise. If corrupted noise is colored. subband approach would be more efficient than whole band one. To avoid serious residual noise and speech distortion, we must adjust the Wavelet Coefficient Threshold (WCT). In this Paper. the subband is designed matching with the critical band and WCT is adapted noise masking threshold (NMT) and segmental signal to noise ratio (seg_SNR). Consequently. it has similar Performance with EVRC in PESQ-MOS. But it's better than wavelet packet transform using universal threshold about 0.289 in PESQ-MOS. The important thing is that it's more useful than EVRC in coded speech. In coded speech. PESQ-MOS is higher than EVRC about 0.23.

Analysis on the Adequate Level of R&D Investment in Small and Medium-sized Enterprises Using Threshold Regression (문턱회귀모형(threshold regression)을 활용한 중소기업의 적정 R&D 투자수준 분석)

  • Jung, Euy-Young;Baek, Chulwoo
    • Journal of Technology Innovation
    • /
    • v.23 no.1
    • /
    • pp.87-105
    • /
    • 2015
  • This research confirms a non-linear relationship between R&D investment and performance of small and medium-sized enterprises and measures the adequate level as threshold value. Although previous studies did not consider the time lag and estimated indirectly the level using the R&D investment squared term, this study assumes 2 years time lag and uses the threshold estimation model to measure directly. We find that there is the S-curve relationship between the profit rate as R&D output and R&D intensity and the ratio of researchers to employees as R&D input. Also, we estimate the adequate levels of R&D investment, 6.4% for R&D intensity and 13% for the ratio of researchers to employees. This relationship and measurement of the level can offer basic facts and implications about R&D policy and strategy.

Analysis of Dimension Dependent Subthreshold Swing for Double Gate FinFET Under 20nm (20nm이하 이중게이트 FinFET의 크기변화에 따른 서브문턱스윙분석)

  • Jeong Hak-Gi;Lee Jong-In;Joung Dong-Su
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2006.05a
    • /
    • pp.865-868
    • /
    • 2006
  • In this paper, the subthreshold swing has been analyzed for double gate FinFET under channel length of 20nm. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel-Framers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained.

  • PDF

Analysis of Dimension Dependent Threshold Voltage Roll-off for Nano Structure Double Gate FinFET (나노구조 이중게이트 FinFET의 크기변화에 따른 문턱전압이동 분석)

  • Jeong Hak-Gi;Lee Jae-Hyung;Joung Dong-Su
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2006.05a
    • /
    • pp.869-872
    • /
    • 2006
  • In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

  • PDF

Analysis of Dimension-Dependent Threshold Voltage Roll-off and DIBL for Nano Structure Double Gate FinFET (나노구조 이중게이트 FinFET의 크기변화에 따른 문턱전압이동 및 DIBL 분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.11 no.4
    • /
    • pp.760-765
    • /
    • 2007
  • In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

Influence of Tunneling Current on Threshold voltage Shift by Channel Length for Asymmetric Double Gate MOSFET (비대칭 DGMOSFET에서 터널링 전류가 채널길이에 따른 문턱전압이동에 미치는 영향)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.20 no.7
    • /
    • pp.1311-1316
    • /
    • 2016
  • This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

Analysis of Threshold Voltage for Symmetric and Asymmetric Oxide Structure of Double Gate MOSFET (이중게이트 MOSFET의 대칭 및 비대칭 산화막 구조에 대한 문턱전압 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.18 no.12
    • /
    • pp.2939-2945
    • /
    • 2014
  • This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.