• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2549-2558
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• 2015

The non-orthogonal multiple access (NOMA) is one of the fledging paradigms which next generation radio access technologies are sprouting toward. The NOMA with superposition coding (SC) in the transmitter and successive interference cancellation (SIC) at the receiver comes with many desirable features and benefits over orthogonal multiple access (OMA) such as orthogonal frequency division multiple access (OFDMA) adopted by Long-Term Evolution (LTE). In this paper, we study the recent research trends on NOMA in 5G systems. We discuss the basic concept of NOMA and explain its aspects of importance for future radio access. Then, we provide a survey of the state of the art in NOMA for 5G systems in a categorized manner. Further, we analyze the NOMA performances with numerical examples; and provide some avenues for future research on NOMA on a set of open issues and challenges.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3C
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• pp.279-285
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• 2006

In this study, a new signal model suitable for UWB indoor environments with random angle spread is proposed to estimate the angle-of-arrivals(AOAs) of UWB cluster signals in an UWB wireless communication. A subspace based estimation technique adopted for this model is investigated and the estimates of the AOA and distribution parameter on the received UWB cluster signals are obtained. The proposed model and estimation technique are verified using computer simulations, and the performance of the estimation error is analyzed.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.323-326
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• 2003

본 논문은 무선 음성/영상 송수신용 RF모듈 설계 및 제작하였다. RF 주파수는 정보통신부에서 고시한 영상전송용 2410, 2430, 3450, 2470MHz 사용하였으며 IF 주파수는 479.5MHz를 사용하였다. 설계 및 제작된 RF 모듈은 FR-4 재질인 유전체 4.6, 두게 0.8mm, 양면구조의 기판을 사용하여 50mm x 40mm 크기로 제작되었다. 설계된 송신기 모듈은 ＋5V 단일전원으로 9±1dBm의 출력과 주파수허용편차 50×10/sup -6/이하, 스퓨리어스 발사강도 기본주파수의 평균전력보다 40dB이하의 성능을 만족하였다. 수신기 모듈은 +5V 단일 전원으로 -80dBm이하의 수신감도로 만족할만한 성능을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.217-223
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• 2003

In spite of widely deploying information broadcasting services based on Internet, there are some limitations to use them due to the bound of Internet protocol. In this paper, a new Internet broadcasting technology for access network is proposed by employing IP address translation function in base station. There are some advantages such as; no need to allocate IP address to receiver, no need to know web site address, and reduction of traffic for server and network. Especially, this technology is very proper to wireless Internet local information broadcasting.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.4
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• pp.55-62
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• 2004

In this paper, we have developed a portable acceleration measurement system to measure acceleration signals during walking and a gait analysis algorithm which can evaluate gait regularity and symmetry and estimate gait parameters automatically. Portable acceleration measurement system consists of a biaxial accelerometer, amplifiers, lowpass filter with cut-off frequency of 16Hz, one-chip microcontroller, EEPROM and RF(TX/RX) module. The algerian includes FFT analysis, filter processing and detection of main peaks. In order to develop the algorithm, eight hemiplegic patients for training set and the other eight hemiplegic patients for test set are participated in the experiment. Acceleration signals during 10m walking were measured at 60 samples/sec from a biaxial accelerometer mounted between L3 and L4 intervertebral area. The algorithm, detected foot contacts and classified right/left steps, and then calculated gait parameters based on these informations. Compared with video data and analysis by manual, algorithm showed good performance in detection of foot contacts and classification of right/left steps in test set perfectly. In the future, with improving the reliability and ability of the algerian so that calculate more gait Parameters accurately, this system and algerian could be used to evaluate improvement of walking ability in hemiplegic patients in clinical practice.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.27-35
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• 2001

Based on the development of mobile communication, the future mobile communication systems are expected to provide higher quality of multimedia services for users than today\`s systems. Therefore, many technical factors are needed in this systems. Especially the secrecy and the safety would be obtained through the introduction of the security for mobile communication. In this paper, we presents a digital nominative proxy signature scheme that processes a user\`s digital signature and encryption using the proxy-agent who has more computational power than origins in mobile communication. The proposed scheme provides non-repudiation and prevents creating illegal signature by the origin and proxy-agent in a phase of proxy signature processing. Also this scheme satisfies the confidentiality and safety in the mobile communication through a confirming signature by the right receiver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.851-856
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• 2006

This paper studies about design of a transceiver using a single PLL. The transceiver has bandwidth of $424.7\sim424.95MHz$ and the communication method used 21 channels 12.5 KHz channel bandwidth and FSK modulation/demodulation method. Also, we designed low power wireless transceiver for data transmission using a single PLL. Finally, the transceiver set achieves the following characteristics : 8.15dBm output power, 45.97dBc spurious property.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.191-197
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• 2012

In this paper we propose the FQSM(Fairness and QoS Supporting MAC) protocol that supports fairness and Quality of Service(QoS). The received or measured data traffics will be assigned a priority level according to its transmission urgency in the FQSM. And the load prediction algorithm is used to support the fairness between different priority traffics. For this, the buffer length values of the nodes are continuously monitored for a some period. Based on the buffer length variations for this period, the order of transmission is determined. FQSM also adapts cross-layer concept to rearrange the data transmission order in each sensor node's buffer, saves energy consumption by allowing few nodes in data transmission, and prolongs the network lifetime.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.