• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.2
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• pp.75-83
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• 2009

This paper presents a new mobile robot localization method for indoor robot navigation. The method uses color-coded landmarks on the ceiling and a camera is installed on the robot facing the ceiling. The proposed "cell-coded map", with the use of only nine different kinds of color-coded landmarks distributed in a particular way, helps reduce the complexity of the landmark structure. This technique is applicable for navigation in an unlimited size of indoor space. The structure of the landmarks and the recognition method are introduced. And 2 rigid rules are also used to ensure the correctness of the recognition. Experimental results prove that the method is useful.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.31-39
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• 2007

In this paper, a system for real-time or periodic measurement and analysis of RF parameters such as forward transmit power and pilot power in CDMA base station systems is proposed. Such RF characteristic parameter measurement can be prevented from system fault and used to achieve optimal service quality and maximum investment return through cell coverage expansion, subscriber capacity increase and so on. For forward power measurement, the local oscillator frequency for the detector is varied so that the transmit power for all channels can be measured. The channel power measurement can be used to analyze the variation in transmit power for changes in voice traffic. By comparing to forward $E_c/I_o$, the pilot channel power can be deducted, which can be used to determine uy degradation in transmit section modules such as the high dover amplifier. Since an accurate analysis of carefully measured data using the CDMA level detector must be made, the system is designed so that measurement errors due to changes in crest factor with modulation method can be overcome.

• Journal of the Korean Electrochemical Society
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• v.16 no.3
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• pp.123-128
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• 2013

Organic carbons such as methanol, ethanol, iso-propanol, methoxy ethanol, glucose are added(1, 2, 3%) in the 2000 ppm $NH_3$ and $H_3PO_4$. As vol.%. cyclic voltammetry measurement of the capacity with the addition of organic carbon, the results of $NH_3$ + 3 vol.% Methanol Addition, $H_3PO_4$ + 2 vol.% iso-propanol addition of the increase in capacity was observed. Applying to the CDI Module cell with an addiction of organic carbon is confirm that remove $NH_4$-N and $PO_4$-P in sewage. Namely, the removal efficiency of $NH_3$ was increase of 16.4% during adsorption, 30.4% during desorption and the removal efficiency of $H_3PO_4$ was increase of 63% during adsorption, 54.7% during desorption. Therefore, the result of this research is confirm that effect of the N, P removal and considered that reduction of the operating costs without removing the organic matter in the influent wastewater.

• Journal of Navigation and Port Research
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• v.29 no.5 s.101
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• pp.415-420
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• 2005

LMTT (Linear Motor-based Transfer Technology) is the horizontal transfer system for yard automation, which has been proposed to take the place of AGV (Automated Guided Vehicle) in the maritime container terminal. The system is based on PMLSM (Permanent Magnetic Linear Synchronous Motor) that consists of stator modules on the rail and shuttle car. It is desirable to reduce the weight of LMTT in order to control the electronic devices with minimum energy. In this research, structural optimization for a mover of shuttle car is performed to minimize the weight satisfying design criteria. The objective function is set up as weight. On the contrary, the design variables are transverse, longitudinal and wheel beams' thicknesses and its height, and the constraints are considered as strength and stiffness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.477-485
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• 2015

Most existing simulators for wireless sensor networks(WSNs) are modeling battery-based sensors and providing MAC and routing protocols designed for battery-based WSNs. However, recently, as energy harvesting sensor systems have been studied more extensively, there is an increasing need for appropriate simulators, but few related studies have employed such simulators. Unlike existing simulators, simulators for energy harvesting WSNs require a new energy model that is integrated with the energy-harvesting model, rechargeable battery model, and energy-consuming model. Additionally, it should enable the applications of the well-known MAC and routing protocols designed for energy-harvesting WSNs, as well as a user-friendly interface for convenience. In this work, we design and implement a user-friendly simulator for solar energy-harvesting WSNs.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.225-234
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• 2019

By using the Triboelectric nanogenerators, known as TENG, we can take advantages of high conversion efficiency and continuous power output even with small vibrating energy sources. Nonlinear energy extraction techniques for Triboelectric vibration energy harvesting usually requires synchronized active electronic switches in most electronic interface circuits. This study presents a nonlinear energy harvesting with high energy conversion efficiency to harvest and save energies from human active motions. Moreover, the proposed design can harvest and store energy from sway motions around different directions on a horizontal plane efficiently. Finally, we conducted a comparative analysis of a multi-mode energy storage board developed by a silicon-based piezoelectricity and a transparent TENG cell. As a result, the experiment showed power generation of about 49.2mW/count from theses multi-fully harvesting source with provision of stable energy storages.

• Transactions of the Korean hydrogen and new energy society
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• v.31 no.6
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• pp.622-629
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• 2020

The performance and cost of electric vehicles (EVs) are much influenced by the performance and service life of the Li-ion battery system. In particular, the cell performance and reliability of Li-ion battery packs are highly dependent on their operating temperature. Therefore, a novel battery thermal management is crucial for Li-ion batteries owing to heat dissipation effects on their performance. Among various types of battery thermal management systems (BTMS'), the phase change material (PCM) based BTMS is considered to be a promising cooling system in terms of guaranteeing the performance and reliability of Li-ion batteries. This work is mainly concerned with the basic research on PCM based BTMS. In this paper, a basic experimental study on PCM based battery cooling system was performed. The main purpose of the present study is to present a comparison of two PCM-based cooling systems (n-Eicosane and n-Docosane) of the unit 18650 battery module. To this end, the simplified PCM-based Li-ion battery module with two 18650 batteries was designed and fabricated. The thermal behavior (such as temperature rise of the battery pack) with various discharge rates (c-rate) was mainly investigated and compared for two types of battery systems employing PCM-based cooling. It is considered that the results obtained from this study provide good fundamental data on screening the appropriate PCMs for future research on PCM based BTMS for EV applications.

• Journal of IKEEE
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• v.24 no.4
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• pp.961-968
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• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.