• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.924-933
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• 2008

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.1-8
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• 2002

Digital image watermarking is a technique for the purpose of protecting the ownership of the image by embedding proprietary watermarks in a digital image. It is required for the digital image watermarking scheme to pursue the robustness against water marking attacks and the perceptual Invisibility more than usual in steganography area, to guarantee not a hidden watermarking algorithm but the publicity of water-marking algorithm details and hidden use of key, which can protect the unauthorized user access from detection. In this paper we propose a new copyright watermarking scheme, which is barred on one-way hash functions using ElGamal functions and modular operations. ElGamal functions are widely used in cryptographic systems. Our watermarking scheme is robust against LSB(least significant bit) attacks and gamma correction attack, and also perceptually invisible. We demonstrate the characteristics of our proposed watermarking scheme through experiments. It is necessary to proceed as the future work the algorithm of achieving at the same time both the pseudo-randomness for the steno-key generation and the asymmetric-key generation.

• Journal of the Institute of Convergence Signal Processing
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• v.18 no.2
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• pp.62-67
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• 2017

In this paper, we propose a fast motion estimation algorithm which is important in performance of video encoding. Even though so many fast algorithms for motion estimation have been published due to tremendous computational amount of full search algorithm, efforts for reducing computations of motion estimation still remain. In the paper, we propose an algorithm that reduces unnecessary computations only, while keeping prediction quality the same as that of the full search. The proposed algorithm does not calculate block matching error for each candidate directly to find motion vectors but divides the calculation procedure into several steps and calculates partial sum of block errors for candidates with high priority. By doing that, we can find the minimum error point early and get the enhancement of calculation speed by reducing unnecessary computations. The proposed algorithm uses smaller computations than conventional fast search algorithms with the same prediction quality as the full search algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.1
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• pp.73-83
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• 2018

There has been increasing interest from NIST and other companies in studying post-quantum cryptography in order to resist against quantum computers. Multivariate polynomial based, code based, lattice based, hash based digital signature, and isogeny based cryptosystems are one of the main categories in post quantum cryptography. Among these categories, isogeny based cryptosystem is known to have shortest key length. In this paper, we implemented Supersingular Isogeny Diffie-Hellman (SIDH) protocol efficiently on low-end mobile device. Considering the device's specification, we select supersingular curve on 523 bit prime field, and generate efficient isogeny computation tree. Our implementation of SIDH module is targeted for 32bit environment.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.247-258
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• 2003

Principal component analysis (PCA) based algorithms form the basis of numerous algorithms and studies in the face recognition literature. PCA is a statistical technique and its incorporation into a face recognition system requires numerous design decisions. We explicitly take the design decisions by in-troducing a generic modular PCA-algorithm since some of these decision ate not documented in the literature We experiment with different implementations of each module, and evaluate the different im-plementations using the September 1996 FERET evaluation protocol (the do facto standard method for evaluating face recognition algorithms). We experiment with (1) changing the illumination normalization procedure; (2) studying effects on algorithm performance of compressing images using JPEG and wavelet compression algorithms; (3) varying the number of eigenvectors in the representation; and (4) changing the similarity measure in classification process. We perform two experiments. In the first experiment, we report performance results on the standard September 1996 FERET large gallery image sets. The result shows that empirical analysis of preprocessing, feature extraction, and matching performance is extremely important in order to produce optimized performance. In the second experiment, we examine variations in algorithm performance based on 100 randomly generated image sets (galleries) of the same size. The result shows that a reasonable threshold for measuring significant difference in performance for the classifiers is 0.10.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.7
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• pp.1367-1372
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• 2007

This paper suggests One-time Password key exchange authentication technique for a strong authentication based on MANET and through identify wireless environment security vulnerabilities, analyzes current authentication techniques. The suggested authentication technique consists of 3 steps: Routing, Registration, and Running. The Routing step sets a safe route using AODV protocol. The Registration and Running step apply the One-time password S/key and the DH-EKE based on the password, for source node authentication. In setting the Session key for safe packet transmission and data encryption, the suggested authentication technique encrypts message as H(pwd) verifiers, performs key exchange and utilizes One time password for the password possession verification and the efficiency enhancement. EKE sets end to end session key using the DH-EKE in which it expounds the identifier to hash function with the modula exponent. A safe session key exchange is possible through encryption of the H(pwd) verifier. The suggested authentication technique requires exponentiation and is applicable in the wireless network environment because it transmits data at a time for key sharing, which proves it is a strong and reliable authentication technique based on the complete MANET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1026-1031
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• 2008

Nowdays, homes and small businesses rely more and more PON(Passive Optical Networks) for financial transactions, private communications and even telemedicine. Thus, encryption for these data transactions is very essential due to the multicast nature of the PON In this parer, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features; 1) Composite field arithmetic SubByte, 2) efficient MixColumn transformation 3) and on-the-fly key-scheduling for fully pipelined architecture. By pipeling the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the on-the-fly key-scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.440-451
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• 2019

We propose a system that allows three dimensional manipulation of face in video. The 3D face manipulation of the proposed system overlays the 3D face model with the user 's manipulation on the face region of the video frame, and it allows 3D manipulation of the video in real time unlike existing applications or methods. To achieve this feature, first, the 3D morphable face model is registered with the image. At the same time, user's manipulation is applied to the registered model. Finally, the frame image mapped to the model as texture, and the texture-mapped and deformed model is rendered. Since this process requires lots of operations, parallel processing is adopted for real-time processing; the system is divided into modules according to functionalities, and each module runs in parallel on each thread. Experimental results show that specific parts of the face in video can be manipulated in real time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.9-14
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• 2019

A small millimeter-wave tracking radar is a pulse-based radar that searches, detects, and tracks a target in real time through a TWS (Track While Scan) method for a traps target on the sea with a large RCS running at low speed. It is necessary to develop a board equipped with a high-speed CPU to acquire and track target information through LPRF, DBS, and HRR signal processing techniques for a trap target operating various kinds of dexterous objects such as chaff and decoy, We designed a signal processor structure including DFT (Discrete Fourier Transform) module design that can perform real - time FFT operation using FPGA (Field Programmable Gate Array) and verified the signal processor implemented through performance test.