• Journal of Korea Game Society
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• v.19 no.4
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• pp.97-108
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• 2019

Recently interests in voice game commands have been increasing due to the diversity and convenience of the input method, but also by the distance between commands. The command distance is the phonetic difference between command utterances, and as such distance increases, the recognition rate improves. In this paper, we propose an IP(Integer Programming) modeling of the problem which is to select a combination of commands from given candidate commands for maximizing the average distance. We also propose a SA(Simulated Annealing)-based algorithm for solving the problem. We analyze the characteristics of our method using experiments under various conditions such as the number of commands, allowable command length, and so on.

• Annual Conference on Human and Language Technology
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• 2023.10a
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• pp.306-311
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• 2023

최근 생성형 언어모델에 명령어 튜닝을 적용하여 사람의 명령을잘이해하고, 대답의 성능을 향상시키는 연구가 활발히 수행되고 있으며, 이 과정에서 다양한 명령어 튜닝 데이터셋이 등장하고 있다. 하지만 많은 데이터셋들 중에서 어떤 것을 선택해서 활용하지가 불분명하기 때문에, 현존하는 연구들에서는 단순히 데이터셋을 모두 활용하는 방식으로 명령어 튜닝이 진행되고 있다. 하지만 최근 연구들에서 고품질의 적은 데이터셋으로도 명령어 튜닝을 하기에 충분하다는 결과들이 보고되고 있는 만큼, 많은 명령어 데이터셋에서 고품질의 명령어를 선별할 필요성이 커지고 있다. 이에 따라 본 논문에서는 한국어 데이터셋에서도 명령어 튜닝 데이터셋의 품질을 향상시키기 위해, 기존의 데이터셋들에서 데이터를 큐레이션하여 확보된 적은 양의 고품질의 명령어 데이터셋인 KoQuality를 제안한다. 또한 KoQuality를 활용하여 한국어 언어모델에 명령어 튜닝을 진행하였으며, 이를 통해 자연어 이해 성능을 높일 수 있음을 보인다. 특히 제로샷 상황에서 KoBEST 벤치마크에서 기존의 모델들보다 높은 성능 향상을 보였다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.715-717
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• 2002

최신의 프로세서는 분기명령에 의한 파이프라인 지연을 피하기 위해 분기 예상 기법을 사용하고 있다. 그러나 예측기에서 예상이 잘못된 경우에는 예상한 분기 방향의 명령어들을 무효화시키고 올바른 분기 방향의 명령어들을 다시 반입하여 수행시키므로 서 수행 사이클과 하드웨어 자원을 낭비하게된다. 본 논문에서는 컴파일 시 프로파일링을 통한 정적인 방법과 프로그램상의 제어 흐름을 통해 동적으로 제어 독립적인 명령어를 탐지해서 분기 명령어의 잘못된 예상으로 인해 무효화되는 명령어를 효과적으로 감소시켜 프로세서의 성능을 향상시키는 메커니즘을 제안한다. SPECint95 벤치마크 프로그램에 대해 기존의 방법과 본 논문에서 제안한 방법 사이의 사이클 당 수행된 명령어 수를 분석한 결과, 4-이슈 프로세서에서 2%-7%, 8-이슈 프로세서에서 4%-l5%, 16-이슈 프로세서에서 18%-28%의 성능 향상을 보이고 있다.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.227-235
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• 2005

In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7％ code size additionally with no performance penalty

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.33-39
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• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

• The Journal of the Convergence on Culture Technology
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• v.5 no.1
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• pp.395-399
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• 2019

In order to support various parallel computing systems, it is necessary to extend LLVM IR to more efficiently support vector / matrix and to design LLVM IR to machine code as a new algorithm. As shown in the IR example, RISC instruction generation is naturally generated because the RISC instruction is basically composed of the RISC instruction, and the vector instruction is also not supported. There is a need for new IR structures, command generation algorithms and related extensions to support vector / matrix more robustly. To do this, it is important to map each instruction in the LLVM IR to the appropriate instruction in the target architecture (vector / matrix) (instruction selection algorithm). It is necessary to understand the meaning of LLVM IR command, to compare the meaning of each instruction of the target architecture with syntax, and to select the instruction that matches the pattern to make mapping efficient.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• The KIPS Transactions:PartA
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• v.19A no.1
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• pp.45-50
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• 2012

The demand for faster execution time and lower energy consumption has compelled architects of embedded processors to customize it to the needs of their target applications. These processors consequently provide a rich set of specialized instructions in order to enable programmers to access these features. Such an instruction is typically a $multi$-$output$ $instruction$ (MOI), which outputs multiple results parallely in order to exploit inherent underlying hardware parallelism. Earlier study has exhibited that MOIs help to enhance performance in aspect of instruction counts and code size. However the earlier algorithm does not consider the register pressure. So, some selected MOIs introduce register spill/reload code that increases the code size and instruction count. To attack this problem, we introduce a novel iterated instruction selection algorithm based on the register pressure of each selected MOIs. The experimental results show the suggested algorithm achieves 3% code-size reduction and 2.7% speed-up on average.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.682-684
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• 2002

최근 여러 논문에서 실 데이터 종속을 제거하기 위하여 결과 값 예상 기법을 제안하였다. 결과 값 예상 기법 중 혼합형 결과 값 예측기는 다양한 패턴을 갖는 명령어를 모두 예측함으로써 높은 예상 정확도를 얻을 수 있지만 하나의 명령어가 여러 개의 예측기 테이블에 중복 저장되어 높은 하드웨어 비용을 요구한다는 단점이 있다. 본 논문에서는 이러한 단점을 극복하기 위하여 프로파일링으로 얻어진 정적 분류 정보를 사용하여, 명령어률 예상 정확도가 높은 예측기에만 할당하여 예상 테이블 크기를 감소 시켰다. 또한 동적으로 적절한 예측기를 선택하도록 함으로써 예상 정확도를 더욱 향상 시켰다. 본 논문에서는 SPECint95 벤치마크 프로그램에 대해 SimpleScalar/PISA 3.0 툴셋을 사용하여 실험하였다. 정적-동적 분류 정보를 모두 사용하였을 경우 87.9%, VHT 크기를 4K로 축소한 경우 87.5%로 비슷한 예상정확도를 얻으면서 예상 테이블의 크기는 50%로 감소하였다. 또한 실행 패턴의 유형 비율에 따라 각 예측기의 VHT를 구성한 경우 예상 테이블 크기를 25%로 줄일 수 있었다.

• The KIPS Transactions:PartA
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• v.14A no.6
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• pp.347-356
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• 2007

In designing a branch predictor, in addition to accuracy, microarchitects should consider power consumption, especially for embedded processors. This paper proposes a power-aware branch predictor, which is based on the gshare predictor, by accessing the BTB (Branch Target Buffer) only when the prediction from the PHT (Pattern History Table) is taken. To enable the selective access to the BTB, the PHT in the proposed branch predictor is accessed one cycle earlier than the traditional PHT to prevent the additional delay. As a side effect, two predictions from the PHT are obtained through one access to the PHT, which leads to more power savings. The proposed branch predictor reduces the power consumption, not requiring any additional storage arrays, not incurring additional delay (except just one MUX delay) and never harming accuracy. Simulation results show that the proposed predictor reduces the power consumption by $35{\sim}48%$ compared to the traditional predictor.