• Title/Summary/Keyword: 메모리 효율

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3D Mesh Reconstruction Technique from Single Image using Deep Learning and Sphere Shape Transformation Method (딥러닝과 구체의 형태 변형 방법을 이용한 단일 이미지에서의 3D Mesh 재구축 기법)

  • Kim, Jeong-Yoon;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.160-168
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    • 2022
  • In this paper, we propose a 3D mesh reconstruction method from a single image using deep learning and a sphere shape transformation method. The proposed method has the following originality that is different from the existing method. First, the position of the vertex of the sphere is modified to be very similar to the 3D point cloud of an object through a deep learning network, unlike the existing method of building edges or faces by connecting nearby points. Because 3D point cloud is used, less memory is required and faster operation is possible because only addition operation is performed between offset value at the vertices of the sphere. Second, the 3D mesh is reconstructed by covering the surface information of the sphere on the modified vertices. Even when the distance between the points of the 3D point cloud created by correcting the position of the vertices of the sphere is not constant, it already has the face information of the sphere called face information of the sphere, which indicates whether the points are connected or not, thereby preventing simplification or loss of expression. can do. In order to evaluate the objective reliability of the proposed method, the experiment was conducted in the same way as in the comparative papers using the ShapeNet dataset, which is an open standard dataset. As a result, the IoU value of the method proposed in this paper was 0.581, and the chamfer distance value was It was calculated as 0.212. The higher the IoU value and the lower the chamfer distance value, the better the results. Therefore, the efficiency of the 3D mesh reconstruction was demonstrated compared to the methods published in other papers.

LSTM Prediction of Streamflow during Peak Rainfall of Piney River (LSTM을 이용한 Piney River유역의 최대강우시 유량예측)

  • Kareem, Kola Yusuff;Seong, Yeonjeong;Jung, Younghun
    • Journal of Korean Society of Disaster and Security
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    • v.14 no.4
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    • pp.17-27
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    • 2021
  • Streamflow prediction is a very vital disaster mitigation approach for effective flood management and water resources planning. Lately, torrential rainfall caused by climate change has been reported to have increased globally, thereby causing enormous infrastructural loss, properties and lives. This study evaluates the contribution of rainfall to streamflow prediction in normal and peak rainfall scenarios, typical of the recent flood at Piney Resort in Vernon, Hickman County, Tennessee, United States. Daily streamflow, water level, and rainfall data for 20 years (2000-2019) from two USGS gage stations (03602500 upstream and 03599500 downstream) of the Piney River watershed were obtained, preprocesssed and fitted with Long short term memory (LSTM) model. Tensorflow and Keras machine learning frameworks were used with Python to predict streamflow values with a sequence size of 14 days, to determine whether the model could have predicted the flooding event in August 21, 2021. Model skill analysis showed that LSTM model with full data (water level, streamflow and rainfall) performed better than the Naive Model except some rainfall models, indicating that only rainfall is insufficient for streamflow prediction. The final LSTM model recorded optimal NSE and RMSE values of 0.68 and 13.84 m3/s and predicted peak flow with the lowest prediction error of 11.6%, indicating that the final model could have predicted the flood on August 24, 2021 given a peak rainfall scenario. Adequate knowledge of rainfall patterns will guide hydrologists and disaster prevention managers in designing efficient early warning systems and policies aimed at mitigating flood risks.

An Approach Using LSTM Model to Forecasting Customer Congestion Based on Indoor Human Tracking (실내 사람 위치 추적 기반 LSTM 모델을 이용한 고객 혼잡 예측 연구)

  • Hee-ju Chae;Kyeong-heon Kwak;Da-yeon Lee;Eunkyung Kim
    • Journal of the Korea Society for Simulation
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    • v.32 no.3
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    • pp.43-53
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    • 2023
  • In this detailed and comprehensive study, our primary focus has been placed on accurately gauging the number of visitors and their real-time locations in commercial spaces. Particularly, in a real cafe, using security cameras, we have developed a system that can offer live updates on available seating and predict future congestion levels. By employing YOLO, a real-time object detection and tracking algorithm, the number of visitors and their respective locations in real-time are also monitored. This information is then used to update a cafe's indoor map, thereby enabling users to easily identify available seating. Moreover, we developed a model that predicts the congestion of a cafe in real time. The sophisticated model, designed to learn visitor count and movement patterns over diverse time intervals, is based on Long Short Term Memory (LSTM) to address the vanishing gradient problem and Sequence-to-Sequence (Seq2Seq) for processing data with temporal relationships. This innovative system has the potential to significantly improve cafe management efficiency and customer satisfaction by delivering reliable predictions of cafe congestion to all users. Our groundbreaking research not only demonstrates the effectiveness and utility of indoor location tracking technology implemented through security cameras but also proposes potential applications in other commercial spaces.

Research on the Design of TPO(Time, Place, 0Occasion)-Shift System for Mobile Multimedia Devices (휴대용 멀티미디어 디바이스를 위한 TPO(Time, Place, Occasion)-Shift 시스템 설계에 대한 연구)

  • Kim, Dae-Jin;Choi, Hong-Sub
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.2
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    • pp.9-16
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    • 2009
  • While the broadband network and multimedia technology are being developed, the commercial market of digital contents as well as using IPTV has been widely spreading. In this background, Time-Shift system is developed for requirement of multimedia. This system is independent of Time but is not independent of Place and Occasion. For solving these problems, in this paper, we propose the TPO(Time, Place, Occasion)-Shift system for mobile multimedia devices. The profile that can be applied to the mobile multimedia devices is much different from that of the setter-box. And general mobile multimedia devices could not have such large memories that is for multimedia data. So it is important to continuously store and manage those multimedia data in limited capacity with mobile device's profile. Therefore we compose the basket in a way using defined time unit and manage these baskets for effective buffer management. In addition. since the file name of basket is made up to include a basket's time information, we can make use of this time information as DTS(Decoding Time Stamp). When some multimedia content is converted to be available for portable multimedia devices, we are able to compose new formatted contents using such DTS information. Using basket based buffer systems, we can compose the contents by real time in mobile multimedia devices and save some memory. In order to see the system's real-time operation and performance, we implemented the proposed TPO-Shift system on the basis of mobile device, MS340. And setter-box are desisted by using directshow player under Windows Vista environment. As a result, we can find the usefulness and real-time operation of the proposed systems.

The Design and implementation of parallel processing system using the $Nios^{(R)}$ II embedded processor ($Nios^{(R)}$ II 임베디드 프로세서를 사용한 병렬처리 시스템의 설계 및 구현)

  • Lee, Si-Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.11
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    • pp.97-103
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    • 2009
  • In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using $Nios^{(R)}$ II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-$70^{(R)}$ reference board. The designed Parallel processing system is master-slave, shared memory and MIMD(Mu1tiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

A new warp scheduling technique for improving the performance of GPUs by utilizing MSHR information (GPU 성능 향상을 위한 MSHR 정보 기반 워프 스케줄링 기법)

  • Kim, Gwang Bok;Kim, Jong Myon;Kim, Cheol Hong
    • The Journal of Korean Institute of Next Generation Computing
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    • v.13 no.3
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    • pp.72-83
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    • 2017
  • GPUs can provide high throughput with latency hiding by executing many warps in parallel. MSHR(Miss Status Holding Registers) for L1 data cache tracks cache miss requests until required data is serviced from lower level memory. In recent GPUs, excessive requests for cache resources cause underutilization problem of GPU resources due to cache resource reservation fails. In this paper, we propose a new warp scheduling technique to reduce stall cycles under MSHR resource shortage. Cache miss rates for each warp is predicted based on the observation that each warp shows similar cache miss rates for long period. The warps showing low miss rates or computation-intensive warps are given high priority to be issued when MSHR is full status. Our proposal improves GPU performance by utilizing cache resource more efficiently based on cache miss rate prediction and monitoring the MSHR entries. According to our experimental results, reservation fail cycles can be reduced by 25.7% and IPC is increased by 6.2% with the proposed scheduling technique compared to loose round robin scheduler.

Real-Time Terrain Visualization with Hierarchical Structure (실시간 시각화를 위한 계층 구조 구축 기법 개발)

  • Park, Chan Su;Suh, Yong Cheol
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.29 no.2D
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    • pp.311-318
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    • 2009
  • Interactive terrain visualization is an important research area with applications in GIS, games, virtual reality, scientific visualization and flight simulators, besides having military use. This is a complex and challenging problem considering that some applications require precise visualizations of huge data sets at real-time rates. In general, the size of data sets makes rendering at real-time difficult since the terrain data cannot fit entirely in memory. In this paper, we suggest the effective Real-time LOD(level-of-detail) algorithm for displaying the huge terrain data and processing mass geometry. We used a hierarchy structure with $4{\times}4$ and $2{\times}2$ tiles for real-time rendering of mass volume DEM which acquired from Digital map, LiDAR, DTM and DSM. Moreover, texture mapping is performed to visualize realistically while displaying height data of normalized Giga Byte level with user oriented terrain information and creating hill shade map using height data to hierarchy tile structure of file type. Large volume of terrain data was transformed to LOD data for real time visualization. This paper show the new LOD algorithm for seamless visualization, high quality, minimize the data loss and maximize the frame speed.

A Case Study of Software Architecture Design by Applying the Quality Attribute-Driven Design Method (품질속성 기반 설계방법을 적용한 소프트웨어 아키텍처 설계 사례연구)

  • Suh, Yong-Suk;Hong, Seok-Boong;Kim, Hyeon-Soo
    • The KIPS Transactions:PartD
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    • v.14D no.1 s.111
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    • pp.121-130
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    • 2007
  • in a software development, the design or architecture prior to implementing the software is essential for the success. This paper presents a case that we successfully designed a software architecture of radiation monitoring system (RMS) for HANARO research reactor currently operating in KAERI by applying the quality attribute-driven design method which is modified from the attribute-driven design (ADD) introduced by Bass[1]. The quality attribute-driven design method consists of following procedures: eliciting functionality and quality requirements of system as architecture drivers, selecting tactics to satisfy the drivers, determining architectures based on the tactics, and implementing and validating the architectures. The availability, maintainability, and interchangeability were elicited as duality requirements, hot-standby dual servers and weak-coupled modulization were selected as tactics, and client-server structure and object-oriented data processing structure were determined at architectures for the RMS. The architecture was implemented using Adroit which is a commercial off-the-shelf software tool and was validated based on performing the function-oriented testing. We found that the design method in this paper is an efficient method for a project which has constraints such as low budget and short period of development time. The architecture will be reused for the development of other RMS in KAERI. Further works are necessary to quantitatively evaluate the architecture.

Performance Analysis of Slave-Side Arbitration Schemes for the Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스를 위한 슬레이브 중심 중재 방식의 성능 분석)

  • Hwang, Soo-Yun;Park, Hyeong-Jun;Jhang, Kyoung-Son
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.5_6
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    • pp.257-266
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    • 2007
  • In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

A Hardware Implementation of the Underlying Field Arithmetic Processor based on Optimized Unit Operation Components for Elliptic Curve Cryptosystems (타원곡선을 암호시스템에 사용되는 최적단위 연산항을 기반으로 한 기저체 연산기의 하드웨어 구현)

  • Jo, Seong-Je;Kwon, Yong-Jin
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.1
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    • pp.88-95
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    • 2002
  • In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.