• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.1-10
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• 2010

Recently heterogeneous storage system such as hybrid hard disk drive (H-HDD) combining flash memory and magnetic disk is launched, according as the read performance of NAND flash memory is enhanced as similar to that of hard disk drive (HDD) and the power consumption of NAND flash memory is reduced less than that of HDD. However, the read and write operations of NAND flash memory are slower than those of rotational disk. Besides, serious overheads are incurred on CPU and main memory in the case that intensive write requests to flash memory are repeatedly occurred. In this paper, we propose the Least Frequently Used-Hot scheme that replaces the data blocks whose reference frequency of read operation is low and update frequency of write operation is high, and the data flushing scheme that rearranges the data blocks into the multi-zone of the rotation disk. Experimental results show that the execution time of the proposed method is 38% faster than those of conventional LRU and LFU block replacement schemes in I/O performance aspect and the proposed method increases the life span of Non-Volatile Cache 40% higher than those of conventional LRU, LFU, FIFO block replacement schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.115-122
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• 2004

This paper describe the implementation or the boot loader for the boot system using of memory card. This boot roader consist of the system initialization, CF card checking, CF memory card checking, file system and the program relocator. This boot loader increase the system stability with program consistency checking algorithm in the read phase from the CF memory card. And this system have the compatibility in CF memory card file system, so system manufacturing productivity increase.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1177-1187
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• 2010

Flash memory becomes popular storage for small devices due to its efficiency, portability, low power consumption and large capacity. Unlike on hard disks, however, write operation on flash memory is much more expensive than read operation, so that it is critical for performance enhancement to reduce the number of executions of write operation. This paper proposes static analysis to rewrite a program to reduce the total number of write operations by merging writable data in a minimum number of pages. To achieve this, we collect information about writable areas by static analysis, and about frequently executed paths by profiling for practicality, and combine both to rewrite the application program to reallocate data. The performance enhancement gained from the proposed methods is shown using a FAST simulator.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.395-404
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• 2010

Solid-State Disks (SSDs) have been currently considered as a promising candidate to replace hard disks, due to their significantly short access time, low power consumption, and shock resistance. SSDs, however, have drawbacks such that their write throughput and life span are decreased by random-writes, nearly regardless of SSDs controller designs. Previous studies have mostly focused on better designs of SSDs controller and reducing the number of write operations to SSDs. We suggest another method that reallocates data pages that tend to be simultaneously written to contiguous blocks. Our method gathers write operations during a period of time and generates write traces. After transforming each trace to a set of transactions, our method mines frequent itemsets from the transactions and reallocates the pages of the frequent itemsets. In addition, we introduce an algorithm that reallocates the pages of the frequent itemsets with moderate time complexity. Experiments using TPC-C workload demonstrated that our method successfully reduce 6% of total logical block access.

• The KIPS Transactions:PartC
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• v.18C no.2
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• pp.89-96
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• 2011

ASR is an excellent program security technique that protects various data memory areas without run-time overhead. ASR hides the addresses of variables from attackers by reordering variables within a data memory area; however, it can be broken by brute force attacks because of a limited data memory space. In this paper, we propose Multiple ASR to overcome the limitation of previous ASR approaches. Multiple ASR separates a data memory area into original and duplicated areas, and compares variables in each memory area to detect an attack. In original and duplicated data memory areas variables are arranged in the opposite order. This makes it impossible to overwrite the same variables in the different data areas in a single attack. Although programs with Multiple ASR show a relatively high run-time overhead due to duplicated execution, programs with many I/O operations such as web servers, a favorite attack target, show 40~50% overhead. In this paper we develop and test a tool that transforms a program into one with Multiple ASR applied.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.51-54
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• 2000

Due to the emerging of high-speed network, lots of interests of access to remote data have increased. Those interests motivate using of Cooperative Caching that uses remote cache like local cache by sharing other clients' cache. The conventional algorithm like GMS(Global Memory Service) has some disadvantages that occurred bottleneck and decreasing performance because of exchanges of many messages to server or manager. On the other hand, Hint-based algorithm resolves a GMS's server bottleneck as each client has hint information of all blocks. But Hint-based algorithm also causes some problems such as inaccurate information in it, if it has too old hint information. In this paper, we offer the policy that supplement bottleneck and inaccuracy； by using file identifier that can search for the lookup table and by exchanging oldest block information between each client periodically.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.5
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• pp.228-235
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• 2001

본 논문에서는 분산메모리를 가진 병렬 컴퓨터에서 밀집 행렬 연산을 위한 PoLAPACK 패키지를 소개한다. PoLAPACK은 새로운 연산 기법을 적용한 LU, QR, Cholesky 인수분해 알고리즘들을 포함하고 있다. 블록순환분산법으로 분산되어 있는 행렬에 알고리즘적인 블록 기법(algorithimic blocking)을 적용하여, 실제 행렬의 분산에 사용된 블록의 크기와 다른, 최대의 성능을 보일 수 있는 최적의 블록 크기로 연산을 수행할 수 있다. 이러한 연산 방식은 분산되어 있는 원래의 행렬 A의 순서를 따르지 않으며, 따라서 최적의 블록 크기로 연산을 수행한 후에 얻어진 해 x를 원래 행렬 분산법을 따라서 재배치하여야 한다. 본 연구는 Cray T3E 컴퓨터에서 구현하였으며 ScaLAPACK의 인수분해 루틴들과 그 성능을 비교.분석하였다.

• Journal of KIISE
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• v.42 no.10
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• pp.1247-1253
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• 2015

An inverted index structure is widely used for efficient string similarity search. One of the main requirements of similarity search is a fast response time; to this end, most techniques use an in-memory index structure. Since the size of an inverted index structure usually very large, however, it is not practical to assume that an index structure will fit into the main memory. To alleviate this problem, we propose a novel technique that reduces the size of an inverted index. In order to reduce the size of an index, the proposed technique rearranges data strings so that the data strings containing the same q-grams can be placed close to one other. Then, the technique encodes those multiple strings into a range. Through an experimental study using real data sets, we show that our technique significantly reduces the size of an inverted index without sacrificing query processing time.

• KIPS Transactions on Software and Data Engineering
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• v.7 no.5
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• pp.177-188
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• 2018

The scale of graph data has been increased rapidly because of the growth of mobile Internet applications and the proliferation of social network services. This brings upon the imminent necessity of efficient distributed and parallel graph processing approach since the size of these large-scale graphs are easily over a capacity of a single machine. Currently, there are two popular parallel graph processing approaches, vertex-centric graph processing and block centric processing. While a vertex-centric graph processing approach can easily be applied to the parallel processing system, a block-centric graph processing approach is proposed to compensate the drawbacks of the vertex-centric approach. In these systems, the initial quality of graph partition affects to the overall performance significantly. However, it is a very difficult problem to divide the graph into optimal states at the initial phase. Thus, several dynamic load balancing techniques have been studied that suggest the progressive partitioning during the graph processing time. In this paper, we present a load balancing algorithms for the block-centric graph processing approach where most of dynamic load balancing techniques are focused on vertex-centric systems. Our proposed algorithm focus on an improvement of the graph partition quality by dynamically reassigning blocks in runtime, and suggests block split strategy for escaping local optimum solution.