• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11A
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• pp.1117-1123
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• 2008

Applications for mobile multimedia are testing the performance limits of present day CPUs with variety. However, hardwired solutions are inflexible and expensive to develop. CPUs with flexibility have limitation of performance. So, the requirement for both ASIC-like performance and CPU-like flexibility has led to reconfigurable processor. Mobile systems require low power and high performance concurrently. In this paper, we propose reconfigurable processor for mobile multimedia with high energy efficiency. Reconfigurable processor with 121MOPS/mW is developed by 130nm CMOS technology. And the processor was simulated for energy efficiency with 539MOPS/mW by 90nm CMOS technology and effective use of instructions. And we tested its applications for multimedia field. We tested the case of inverse MDCT for MP3 and DF for MPEG4 and ME for H.264.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.11-23
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• 2000

Multicarrier DS-CDMA is an effective approach to realize wideband CDMA system in a multipath fading channel. In this paper, we propose a convolutionally-coded overlapped multicarrier DS-CDMA system, and analyze the performance with subband overlapping variation to determine the overlapping percentage showing best performance. Given a total number of subcarriers M*R, we will show that the BER variation is highly dependent on the rolloff factor P of raised-cosine chip wave-shaping filter irrespective of convolutional encoding rate I/M and repetition coding rate 1/R. We also analyze the possibility of reduction in total MUI by considering both variation of a rolloff factor (0 ($\beta$ :1) and variation of subband overlapping factor (0 ( A :2), and show that the proposed system may outperform the multicarrier DS-CDMA system in [1, 12].

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.107-114
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• 2004

This paper presents block and timing diagrams of the DWA(Data Weighted Averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the MATLAB modeling, the optimized coefficients of the integrators are obtained to design the modulator. The fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed third-order multibit modulator is fabricated in a 0.35${\mu}{\textrm}{m}$ CMOS process. The modulator achieves 75dB signal-to-noise ratio and 74dB dynamic range at 1.2Vp-p 825kHz input signal and 52.8MHE sampling frequency.

• Journal of Korea Multimedia Society
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• v.4 no.4
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• pp.349-355
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• 2001

In this paper, we newly propose a performance enhanced CSMA/CD MAC(Medium Access Control) protocol for the Ethernet which changes its operation mode dynamically according to the network status, not fixed it as one of p-persistent mode and non-persistent mode. Dynamic mode change occurs independently on each node, and uses the consecutive success count and the fail count of the frame transmission. The simulation result shows that the dynamic mode change maintains the enhanced network utilization and transmission delay characteristics. Also we show the implementation simplicity of our MAC protocol through its conceptual design using the Ethernet commercial chip as it stands.

• Journal of Korea Multimedia Society
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• v.13 no.2
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• pp.171-178
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• 2010

The surveillance system in general, has been sufficiently studied in the field of wireless semiconductor using basic sensors and its study of image surveillance system mainly using camera as a sensor has especially been fully implemented. In this paper, we propose 'Intelligent Image Detection System' used by image object identification technique based on the result analysis of various researches. This 'Intelligent Image Detection System' can easily trace and judge before and after a particular incident and ensure affirmative evidence and numerous relative information. Therefore, the 'Intelligent Image Detection System' proposed in this paper can be effectively used in the lived society such as traffic management, disaster alarm system and etc.

• The Journal of the Acoustical Society of Korea
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• v.20 no.8
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• pp.19-23
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• 2001

DSP-based implementation is pervasive in wireless communication parts for systems and handsets according to developing high-speed and low-power programmable Digital Signal Processor (DSP). In this paper, we present a real-time implementation of multi-channel Adaptive Multi-rate (AMR) speech coder. The real-time implementation of an AMR algorithm is achieved using 32-bit fixed-point TMS320C6202 DSP chip that operates at 250 MHz. We performed cross compile, linear assembly optimization and TMS320C62xx assembly optimization for real-time implementation. Furthermore, speech data input/output function and communication function with external CPU is included in an AMR speech coder. The AMR Speech coder developed using DSP EVM board was evaluated in ETRI IMT-2000 Test-bed system.

• Journal of Korea Multimedia Society
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• v.4 no.6
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• pp.570-578
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• 2001

Boundary scan architecture test methodology was introduced to facilitate the testing of complex printed circuit board. The boundary scan architecture has a tremendous potential for real time monitoring of the operational status of a system without interference of normal system operation. In this paper, a new type of embedded controller for real time monitoring of the operational status of a system is proposed and designed by using boundary scan architecture. The proposed real time monitoring embedded controller consists of test access port controller and an embedded controller proposed real time monitoring embedded controller using boundary scan architecture can save the hard-wire resource and can easily interface with boundary scan architecture chip. Experimental results show that the real time monitoring using proposed embedded controller is more effective then the real time monitoring using host computer.

• Journal of Korea Multimedia Society
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• v.14 no.8
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• pp.1029-1040
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• 2011

Electronic identity (e-ID) card based on smartcard is a representative identity credential for on-line and off-line personal identification. The e-ID card can store the personal identity information securely, so that the information can be accessed fast, automated identity verification and used to determine the cardholder's authorization to access protected resources. Due to such features of an e-ID card, the number of government organizations and corporate enterprises that consider using e-ID card for identity management is increasing. In this paper, we present an authentication framework for access control system using e-ID cards by discussing the threat environment and security requirement against e-ID card. Specifically, to accomplish our purpose, we consider the Personal Identity Verification system as our target model.