• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2523-2529
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• 2014

Location estimation service can be provided outdoors using various location estimation system based on GPS. However, location estimation system is based on existing indoor resources as GPS cannot be used because of insufficient visible satellites and weak signals. The fingerprinting technique that uses WLAN signal, in particular, is good to use indoors because it uses RSSI provided by AP to estimate location. However, its accuracy may vary depending on how accurate data the offline stage used where the fingerprinting map is built. The study sampled various data at the stage that builds the fingerprinting map and suggested a location estimation system that enhances its precision by saving the data of high frequency among them to improve this problem. The suggested location estimation system based on majority sampling data estimates location by filtering RSSI data of the highest frequency at the client and server to be saved at a map, building the map and measuring a similar distance. As a result of the test, the location estimation precision stood at minimum 87.5 % and maximum 90.4% with the margin of error at minimum 0.25 to 2.72m.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.