• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.8
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• pp.701-706
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• 2014

In these days, there have been numerous researches on nano and micro satellites under the slogan of "Faster, Smaller, Better, Cheaper". Since optical structure occupies large portion of satellite volume, research on deployable optical structure gains great attention to reduce total volume of the satellite. In this paper, we establish the requirement of deployable optical structure based on specification of conventional optical structure and propose two candidate mechanisms which can satisfy the degree of deployment precision. Then, in order to evaluate the degree of deployment precision, we carry out kinematic analysis on de-space among tilt, de-space and de-center which influences optical characteristic of a satellite.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.408-414
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• 2005

The VCDRO(Voltage Controlled Dielectric Resonate. Oscillator) with low phase noise is designed using nonlinear analysis, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise performance, and the quality factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCDRO and the reliability analysis is accomplished to estimate the probability of operation at the end of life. The developed VCDRO has the oscillating tuning factor of 0.56MHZ1V for the control voltage range of 0-l2V. This VCDRO requires the DC power of 136mW. The phase noise characteristics exhibit good performances of -94.18dBc/Hz (a)10KHz and -116.3dBc/Hz (a)100KHz. And, the output power over 7.33dBm is measured.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.828-834
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• 2009

To get a better profit, standalone mobile game market shifts network-based mobile game. Currently, most of the game platform are separated into mobile to mobile, desktop to desktop, and console to console. Multi platform network game has a diverse problems including consistency control, object management technique, and bandwidth inconsistency. n this paper, we will introduce a multi-platform arcade game "Push-Push", which is played on desktop to mobile environment. The game guarantees realtime play between heterogeneous machine users and game item sharing between two platforms. e will focus n the issues of the 3rd generation multi platform games and propose some techniques or solving these problems. Our server database is implemented on MS SQL database, also the desktop programming tool is Visual Basic, and WIPI(Wireless Internet Platform or Interoperability) as a mobile platform.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1133-1136
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• 2011

In this paper, we proposed a collinear antenna with a stripline structure for IEEE 802.11b/g applications in ISM (Industrial, Scientific, Medical) band of 2.4~2.5 GHz, which supplements disadvantages of COCO(Coaxial Collinear) antenna and OMA(Omnidirectional planar Microstrip Antenna). By using the proposed 4-layer substrate, we obtained improved performances and advantages in production compared with the existing antenna. In order to get antenna arrays, the same phase structure is designed by alternatively connecting outer conductor to inner conductor with ${\lambda}$/2 antenna element, and the substrate of FR4 epoxy (${\epsilon}_r$=4.4, tan${\delta}$=0.02) was used for the actual implementation. The maximum gain of about 4.93 dBi was measured, which leaded to a little improved gain of 0.33 dBi in comparison to the existing OMA structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.21-30
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• 1990

This paper describes a hardware implementation of the interframe monochrome video CODEC using a MC-CVQ(Motion Compensated and Classified Vector Quantization) algorithm. The specifications of this CODEC are (1) the resolution of image is $128{\times}128$ pixels, and (2) the transmission rates are about 10frames/sec at the 64Kbps channel. In order to design the CODEC under these conditions, it is implemented by a multiprocessor system composed of MC unit, CVQ nuit and decoder unit, which are controlled by microprogramming technique. And the 3~stage pipelined ALU(Arithmetic and Logic Unit) is adopted to calculate the minimum error distance in the MC unit and CVQ nuit. The realized system shows that the transmission rates are 6-15 frames/sec according to the relative motion of the video signal.

• Journal of Educational Research in Mathematics
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• v.15 no.4
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• pp.489-504
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• 2005

In this paper, we design a environment in computers and mathematics education. For this purpose, we study two different points of view about relations between computers and mathematics education. As theoretical background, we also study constructionism and microworld. Next, we introduce functionization as a basic principle for computers and mathematics education. The concept of functionization focuses on the variation of mathematical objects, and it is a basic concept of both mathematics and computer science. We consider the concept of functionization as a paradigm for the research and practice of the computers and mathematics education. We also present the concept of functionization as a principle for designing a computer environment. Finally, we use the concept of functionization to integrate two famous microworlds, LOGO and DGS by introducing such objects as tiles and folding nets. Combining LOGO and DGS, we design a new microworld that can be used under the internet environment. We present tiles and folding nets to introduce how the concept of functionization is used to design a new microworld and to integrate two microworids.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.6
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• pp.509-515
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• 2009

In this paper, we analyzed and evaluated noise suppression characteristic of EM wave absorber. We fabricated several absorber samples in different ratios of Sendust and Amorphous with CPE(Chlorinated Ploy-ethylene) as binder and calculated material constants by measured S-parameter. Then, we confirmed that the noise suppression characteristic of EM wave absorbers using microstrip line. A microstrip line with EM wave absorber placed on its top was used to evaluate the conduction noise suppression. As a result, noise suppression effect show different charateristic by changing relative permeability. Therefore, EM wave absorber using Sendust show excellent characteristic. In particular the maximum power absorption over 90 % in 1.7 GHz to over 6 GHz has obtained when composition of Sendust:CPE=80:20wt.%.

• The Journal of the Korea Contents Association
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• v.11 no.2
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• pp.195-203
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• 2011

This case study is based on a fundamental class actually done in the film and video department in Sungkyul University. It aimed at suggesting supportive role for typical film production class in universities in Korea. The list of film styles mentioned in this text is selected from the actual ones for the class and it is focused on utilization of sound and camera. It is ultimately designed to guide students to actual making films. First of all, for example, with a humble camcoder, students are encouraged to record both image and his/her narration which is directly recorded into the built-in microphone. Also directional microphone could be used to experience various positions of 'point-of-hearing'. Regarding camera movements, only distinctive ones out of typical utilization are selected to be dealt with. The movements created by moving vehicle such as dolly or crane beyond the limit of human ability could bring up high imagination of students on movement, besides this could be also easily applied to them for using hand-held technique instead of vehicle. This attitude acquired through the course is important for gettig over the resistance they might have before actual experiencing machinary use in production.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.