• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.852-855
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• 2012

A DC-DC converter for EEPROM IPs which perfom erasing by the FN (Fowler-Nordheim) tunneling and programming by the band-to-band tunneling is designed in this paper. For the DC-DC converter for EEPROM IPs using a low voltage of $1.5V{\pm}10%$ as the logic voltage, a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD ($=3.1V{\pm}0.1V$) is a regulated voltage by a voltage regulator using an external voltage of 5V. The designed DC-DC converter outputs VPP (=8V) and VNN (=-8V) in the write mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.35-40
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• 2012

This paper has proposed a 3~5 GHz IR-UWB low power transmitter for range detection application. Proposed transmitter which has been implemented in a $0.13{\mu}m$ CMOS technology is all digital circuit that consist of simple digital logic. this feature insure low complexity and low power consumption. In addition, center frequency can be changed by adopting voltage controlled delay cell for avoiding existing another radio frequency in UWB low band. Proposed circuit consume only 10pJ/b from 1.2 V supply voltage. The simulation results show 3.3~4.3 GHz center frequency controllability, -51 dBm/MHz maximum output power and is satisfied with FCC regulation.

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.560-567
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• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.6
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• pp.3821-3826
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• 2014

This paper proposes a methodology for developing the performance of a solenoid valve for vehicles based on the dynamic analysis model by an electromagnetic field. The high performance solenoid model with a low current and high thrust was induced through the shape optimal design of the yoke and plunger. To perform the dynamic analysis of the solenoid valve, the input current profile was analyzed. The speed and thrust information was analyzed by FEM with this current profile. The co-simulation method of the circuit model of control logic and electromagnetic model of the solenoid valve was also proposed to analyze the performance with several current patterns. Finally, the performance of the original model and optimal one was compared.

• The Journal of the Acoustical Society of Korea
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• v.17 no.4
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• pp.14-22
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• 1998

본 연구에서는 Texas Instruments 사의 저가형 부동소수점 디지털 신호 처리기 (Digital Singnal Processor, DSP)인 TMS320C32를 이용하여 실시간 화자종속 음성인식 하 드웨어 모듈(VR32)을 개발하였다. 하드웨어 모듈의 구성은 40MHz의 TMS320C32 DSP, 14bit 코덱인 TLC32044(또는 8bit μ-law PCM 코덱), EPROM과 SRAM 등의 메모리와 호 스트 인터페이스를 위한 로직 회로로 이루어졌다. 뿐만 아니라 이 하드웨어 모듈을 PC사에 서 평가해보기 위한 PC 인터페이스용 보드 및 소프트웨어도 개발하였다. 음성인식 알고리 즘의 구성은 에너지와 ZCR을 기반으로 한 끝점검출(Endpoint Detection) 침 10차 가중 LPC 켑스터럼(Weighted LPC Cepstrum) 분석이 실시간으로 이루어지며 이후 Dynamic Time Warping(DTW)를 통하여 최고 유사 단어를 결정하고 다시 검증과정을 거쳐 최종 인식을 수행한다. 끝점검출의 경우 적응 문턱값(Adaptive threshold)을 이용하여 잡음에 강인한 끝 점검출이 가능하며 DTW 알고리즘의 경우 C 및 어셈블리를 이용한 최적화를 통하여 계산 속도를 대폭 개선하였다. 현재 인식률은 일반 사무실 환경에서 통상 단축다이얼 용도로 사 용할 수 있는 30 단어에 대하여 95% 이상으로 매우 높은 편이며, 특히 배경음악이나 자동 차 소음과 같은 잡음환경에서도 잘 동작한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.86-93
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• 2008

The multi-mode terminal modem which is capable of accommodating a variety of wireless communication standards needs versatile arithmetic units for processing a variety of word lengths and wide range of data rates. Since the target hardware is usually designed to meet the required highest performance, it is often wasteful in power consumption especially when low rate data processing cases. Thus, a speed and power adaptability of the arithmetic unit is a desirable feature for the wireless applications. In this paper, we propose a power efficient versatile adder architecture with carry skip logic as a basic building block constructed in hierarchical manner. The validity of the architecture is shown with respect to size, performance, and power efficiency in diverse operating modes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.