• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.1
• /
• pp.170-178
• /
• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.37 no.12
• /
• pp.1238-1244
• /
• 2009

This work proposes a GUI-type on-line diagnostic program using SIMULINK and Fuzzy-Neuro algorithms for a helicopter turboshaft engine. During development of the diagnostic program, a look-up table type base performance module for reducing computer calculating time and a signal generation module for simulating real time performance data are used. This program is composed of the on-line condition monitoring program to monitor on-line measuring performance condition, the fuzzy inference system to isolate the faults from measuring data and the neural network to quantify the isolated faults. The reliability and capability of the proposed on-line diagnostic program were confirmed through application to the helicopter engine health monitoring.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.1
• /
• pp.70-75
• /
• 2014

This paper presents a IR-UWB(Impulse Radio Ultra-Wide Band) transceiver circuit for data communication and real time location system. The UWB receiver is designed to OOK(On-Off Keying) modulation for energy detection. The UWB pulse generator is designed by digital logic. And the Gaussian filter is adopted to reject side lobe in transmitter. The measured sensitivity of the receiver is -65 dBm at 4 GHz with 1 Mbps PRF(Pulse Repetition Frequency). And the measured energy efficiency per pulse is 20.6 pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5 mA and 25.5 mA, respectively, at 1.8 V supply.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.22 no.5
• /
• pp.533-539
• /
• 2012

The purpose of this study is to estimate a validity of control signal through a design of Exoskeleton Robot Arm's capable of intelligent recognition as a human arm's motion by using realtime processed data of generated EMG signals. By an intelligent algorithm, the EMG output value of human biceps and triceps muscles contraction can be recognized and used for the control over exoskeleton arm corresponding to human's recognition and judgement. The EMG sensing data of muscles contraction and relaxation are used as the input signal from human's body to operate the Exoskeleton Robot Arm thus copying human arm motion. An intelligent control of Exoskeleton Robot Arm is to design the analog control circuit which processes the input data, and then to manufacture an integrated control board. And then abstracted signal is passed by DSP signal processing, Fuzzy logic algorithm is designed for a accurate prediction of weight or load through the intelligent algorithm, and design an Exoskeleton Robot Arm to express a human's intention.

• Journal of IKEEE
• /
• v.24 no.1
• /
• pp.319-325
• /
• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.7
• /
• pp.38-44
• /
• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.7
• /
• pp.1371-1378
• /
• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of Advanced Navigation Technology
• /
• v.24 no.4
• /
• pp.314-321
• /
• 2020

Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.60-67
• /
• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.21-27
• /
• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.