• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.329-332
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• 2008

Type-2 퍼지 집합은 언어적인 불확실성을 다루기 위하여 Zadeh에 의해 제안되었고 Mendel과 Kamik에 의해 이론이 체계화 되었다. TSK 퍼지 로직 시스템(TSK Fuzzy Logic Systems; TSK FLS)은 Mamdni 모델과 함께 가장 널리 사용되는 퍼지 로직 시스템이다. 본 논문에서는 Type-2 퍼지 집합을 이용하여 전반부 멤버쉽 함수를 구성하고 후반부 다항식 함수를 상수와 1차식, 2차식으로 확장한 다항식 Type-2 TSK FLS 설계한다. 또한 가스로 공정 데이터에 응용하여 후반부 다항식의 변화에 따른 Type-2 TSK FLS의 특징을 비교 분석 할 뿐 만 아니라 테스트 데이터에 노이즈를 첨가하여 노이즈에 따른 Type-l TSK FLS과 Type-2 TSK FLS의 특성을 분석한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.80-86
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• 2009

In this paper, we present a new charge pump circuit feasible for the implementation with standard twin-well CMOS process technology. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned on during each half of clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. The performance comparison by simulations and measurements demonstrates that the proposed charge pump exhibits the higher output voltage, the larger output current and a better power efficiency over the traditional twin-well charge pumps.

• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.1-9
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• 2008

Proposed in the paper is an automated procedure to construct a plant model for PLC simulation. Since PLC programs only contain the control logic without the information on the plant model, it is necessary to build the corresponding plant model to perform simulation. Conventionally, a plant model for PLC simulation has been constructed manually, and it requires much efforts as well as the in-depth knowledge of simulation. As a remedy for the problem, we propose an automated procedure to generate a plant model from the symbol table of a PLC program. To do so, we propose a naming rule for PLC symbols so that the symbol names include enough information on the plant model. By analyzing such symbol names, we extract a plant model automatically. The proposed methodology has been implemented, and test runs were made.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.8
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• pp.3644-3653
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• 2011

This study proposes the automation of disinfection process in water treat plant to reach target effluent chlorine concentration rate according to chlorine consumption rate by varying travel time. Hydraulic analysis about the process and local facility was surveyed first and the program for automatic operation was developed to solve current problem, whose applied result was presented and proved to be better than present controller. Especially using multi variable process algorithm, the correlation coefficient is analyzed between environment factor and reaction time, and process control prove to be stable through model estimation with optimal control input.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• The Magazine of the IEIE
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• v.29 no.1
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• pp.66-72
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• 2002

VLSI 기술의 발전은 보다 많은 양의 로직을 단일 칩에 집적 가능하게 했고, 이는 System-on-a-chip 시대의 도래를 가능하게 했다. System-on-a-chip을 가능하게 하기 위해서는 많은 종류의 IP (Intellectual Property)가 필요하고, 공정 변환을 쉽게 하기 위해서는 합성이 가능한 RTL 설계가 절실히 요구된다. 본 논문은 이러한 요구에 부응하기 위해서 hard macro 형태의 기존의 IP로 부터 합성 가능한 IP를 자동 생성해 주는 ART(Automatic RTL Translation)로 명명된 기법에 관한 것이다. 제안된 ART 기법을 이용하여 80C52 호환의 8-bit MCU(Micro-controller Unit)의 합성 가능한 RTL model을 자동 생성하였고, 개발된 Soft IP를 이용하여 TCP/IP 전용 MCU를 표함해서 다양한 제품들을 개발하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.3-4
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• 2008

로직 디바이스에서는 알루미늄을 대신하여 구리로 backend-of-line(BEOL) 금속화공정이 대체되고 있다. 그러나 메모리 디바이스에서 구리 배선으로의 전환이 쉽지 않다. Cu-seed layer는 구리 배선을 메모리 디바이스에 적용하기 위해서 필요한 gap-fill 확장성을 개선하기 위한 중요한 부분을 차지한다. Cu-seed layer 증착을 위한 향상된 PVD 장비인 Eni 스퍼터를 소개한다.