• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.237-241
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• 2005

In Bluetooth version 1.0, the frequency hopping algorithm was such that there was one piconet, using a specific frequency, resolving the frequency depending on the part of the digits of the device clock and the Bluetooth address. Basic pattern was a kind of a round-robin using 79 frequencies in the ISM band. At this point, a problem occurs if there were more than two devices using the same frequency within specific range. In this paper, we proposed a software-based adaptive frequency hopping method so that more than two wireless devices can stay connected without frequency crash. Suggested method was implemented with HDL(Hardware Description Language) and automatically synthesized and laid out. Implemented adaptive frequency hopping circuit operated well in 24MHz correctly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.6
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• pp.38-44
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• 2002

Today most companies are designing their automobile shapes by using 3 dimensional CAD software, CATIA. And they used to design 2 dimensional press dies to do some elastic work on their products, but they are currently trying to make use of 3 dimensional software, Pro-Engineer. In this case, they have to change the 3 dimensional product design data to the proper format data for the following process. This paper will show the data loss and the deformation during data transfer between CATIA and Pro-Engineer, and then suggest a solution for these problems. Product's surface will be automatically placed by automatic press tipping angle setting in CATIA to prevent the product from being stuck m the press die. The 2 dimensional section view which is based on the tipping angle setting is created by Z-map. And, to remove the data loss and the data deformation in Pro-Engineer, the product surface are delivered to the next process after it is changed to the 2 dimensional Z-map curves in CATIA. Finally, this paper suggests an algorithm to develop the automatic design program for the press layout which regenerates product shape surface from the previous process.

• KIISE Transactions on Computing Practices
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• v.24 no.1
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• pp.40-45
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• 2018

With the advent of big data and social networks, large-scale graph processing becomes popular research topic. Recently, an optimization technique called Gorder has been proposed to improve the performance of in-memory graph processing. This technique improves performance by optimizing the graph layout on memory to have better cache locality. However, since it is designed for in-memory graph processing systems, the technique is not suitable for disk-based graph engines; also the cost for applying the technique is significantly high. To solve the problem, we propose a new graph ordering called I/O Order. I/O Order considers the characteristics of I/O accesses for SSDs and HDDs to improve the performance of disk-based graph engine. In addition, the algorithmic complexity of I/O Order is simple compared to Gorder, hence it is cheaper to apply I/O Ordering. I/O order reduces the cost of pre-processing up to 9.6 times compared to that of Gorder's, still its performance is 2 times higher compared to the Random in low-locality graph algorithms.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.80-89
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• 2006

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.

• Journal of the Society of Naval Architects of Korea
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• v.55 no.1
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• pp.9-21
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• 2018

Survivability of naval vessels is defined as the ability to perform functions and missions in a combat environment. Survivability has close relationship with the spatial layout of naval vessels. In order to maximize survivability, it must be considered from the early stage of design. However the existing concept of survivability was intended to be applied to unit vessels. So it was not suitable for assessment of spatial layout results at the early stage of design. In this paper, a simplified assessment method which can evaluate the spatial layout considering the survivability in the early stage of design has been proposed. For this, assessment layers were defined on survivability components such as susceptibility, vulnerability, and recoverability. Assessment layers of each component were overlapped to deduce a survivability layer of spatial layout alternatives. In addition, the proposed method and optimization algorithm were used to derive optimal spatial layout alternatives considering survivability.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.41-50
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• 2011

Code obfuscation has been proposed to protect codes in a program from malicious software reverse engineering. It converts a program into an equivalent one that is more difficult to understand the program. Code obfuscation has been classified into various obfuscation technique such as layout, data, control, by obfuscating goals. In those obfuscation techniques, control obfuscation is intended to complicate the control flow in a program to protect abstract information of control flow. For protecting control flow in a program, various control obfuscation transformation techniques have been proposed. However, strategies for effectively applying a control flow obfuscation to program have not been proposed yet. In this paper, we proposed a obfuscation strategy that effectively applies a control flow obfuscation transformation to a program. We conducted experiment to show that the proposed obfuscation strategy is useful for applying a control flow transformation to a program.