• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.10-15
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• 2012

This letter proposes a low-leakage SRAM using power-gating and voltage-level control. The power-gating scheme significantly reduces leakage power by shutting off the power supply to blank memory cell blocks. The voltage-level control scheme saves leakage power by raising the ground line voltage of SRAM cells and word line decoders in data-stored memory cell blocks. A $4K{\times}8bit$ SRAM chip was fabricated using a 1.2V $0.13{\mu}m$ CMOS process. The leakage powers are $1.23{\sim}9.87{\mu}W$ and $1.23{\sim}3.01{\mu}W$ for 0~100% memory usage in active and sleep modes, respectively. During the sleep mode, the proposed SRAM consumes 12.5~30.5% leakage power compared to the conventional SRAM.

• The Journal of the Acoustical Society of Korea
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• v.32 no.4
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• pp.287-293
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• 2013

We present a parametric array signal generating system using $3{\times}16$ transducer array which is composed of multi-resonant frequency transducers of 20kHz and 32.5kHz. To drive transducer array, sixteen channel amplifier using LM1875 chips is designed and implemented, and the PXI system based on the LabView 8.6 for arbitrary signal generation and analysis is used. Using the proposed system, we measure sound pressure level and beam pattern of difference frequency and verify the nonlinear effect of difference frequency. The theoretical absorption range and the Rayleigh distance are 15.51m and 1.933m, respectively and we verify that sound pressure of difference frequency is accumulated and increased at the near-field shorter than the Rayleigh distance. We verify that the beam pattern of the measured difference frequency and the beam pattern obtained by the superposition of two primary frequencies are similar, and high directional parametric signal was generated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.36 no.3
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• pp.195-201
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• 2000

This paper discusses methods for the stable bottom detection and the optimum bottom offset which enable to separate the fish echoes from the bottom echoes with echo integration of demersal fish. In preprocessing of the echo signal, the bottom detection has to be done stably against the fluctuation of echo level and the bottom offset has to be set to a minimum height such that near bottom fish echoes are included Two methods of bottom detection, namely echo level threshold method and maximum echo slope method were compared and analyzed. The echo level method works well if the ideal threshold level was given but it sometimes misses the bottom because of the fluctuation of the echo. Another method to detect the bottom which uses maximum echo slope indicates the simple and stable bottom detection. In addition, the bottom offset has to be set near to the bottom but not to include the bottom echo. Optimum bottom offset should be set a few samples before the detected bottom echo which relates the beginning of pulse shape and acoustic beam pattern to the bottom feature.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.116-123
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• 2007

This paper proposed a new amplitude width modulation for OLED data driver IC. The data driver controls brightness of OLED by adjusting amplitude and width of the data drive current pulse. There were two conventional methods; pulse amplitude modulation(PAM) and pulse width modulation(PWM). The PWM method suffered from lower light emitting time efficiency at low luminance signal. The PAM method suffered from large chip area using DACs for each column. The proposed method was aiming at accurately controlling of the current level by MSB data and light emitting efficiency by LSB data to improve the inefficiencies of the PAM and a PWM. The proposed AWM driver circuit implemented using $0.35-{\mu}m$ 3-poly 4-metal CMOS high voltage process. The simulation result shows the improvement in the accuracy of the gray level control even though the driver circuit is smaller than the PAM.

• Journal of Korea Multimedia Society
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• v.8 no.1
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• pp.9-18
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• 2005

This paper presents the method of calculating the quantization level of the intra-frame in MPEG-4 video encoder. The intra-frame is an essential part in that the quality of the whole GOP is affected by the quality of this frame since the intra-frame, which works as a reference frame within GOP, continuously propagates through other frames. This work proposes how to use bits assigned for gaining the quantization level of the intra-frame, complexity of input images, and GOP structures. The result shows that while existing approaches have the decline in efficiency by using fixed values or show different qualifies depending on the characteristics of the images, the current approach shows the steady results in various images. Comparing with Q2 algorithm obtained in MPEG-4 VM, the approach suggested in this paper gains the benefit of maximum 3.49dB with some variations depending on the characteristics of the images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.3
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• pp.127-139
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• 2014

In this paper, we present two signal processing techniques for designing binary error correction codes for Multi-Level Cell(MLC) NAND flash memory. MLC NAND flash memory saves the non-binary symbol at each cell and shows asymmetric channel LLR l-density which makes it difficult to design soft-decision binary error correction codes such as LDPC codes and Polar codes. Therefore, we apply density mirroring and EM algorithm for approximating the MLC NAND flash memory channel to the binary-input memoryless channel. The density mirroring processes channel LLRs to satisfy roughly all-zero codeword assumption, and then EM algorithm is applied to l-density after density mirroring for approximating it to mixture of symmetric Gaussian densities. These two signal processing techniques make it possible to use conventional code design algorithms, such as density evolution and EXIT chart, for MLC NAND flash memory channel.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.47-54
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• 2008

In this paper, we studied how and why did abnormal IMC growth at component affect on board level mechanical reliability. First, interfacial reactions between Sn2.5Ag0.5Cu solder and electrolytic Ni/Au UBM of component side were investigated with reflow times and thermal aging time. Also, to compare mechanical reliability of component level, shear energy was evaluated using the ball shear test conducted with variation of shear tip speed. Finally, to evaluate mechanical reliability of board level, we surface-mounted component fabricated with each condition on PCB side. After conducting of 3 point bending test and impact test, we confirmed solder joint crack mode using cross-sectioning and dye & pry penetration method.