• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.1157-1164
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• 2003

Dynamic Load/unload (L/UL) mechanism is an alternative to the contact start stop (CSS) technology which eliminates stiction and wear failure modes associated with CSS. Other benefits of L/UL include increased areal density due to smooth disk surfaces, thinner overcoats, and lower head flying height Improved shock resistance due to elimination of head slap, and reduced power consumption. Inertia latch mechanism becomes important for mobile disk drives because of non operating shock performance. Various types of latch designs have been introduced in hard disk drives to limit a rotary actuator from sudden uncontrolled motion. In this paper, a single spring inertia latch is introduced for a small form optical disk drive, which uses a rotary actuator for moving an optical pick-up. A new small inertia latch with single spring is designed to ensure both feasible and small size. The shock performance of the new inertia latch is experimentally verified.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.26-33
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• 1984

This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04b
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• pp.131-133
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• 2000

이 논문에서는 다차원 색인 구조에서 질의를 지연시키는 주된 요인인 노드 분할연산과 MBR(Minimun Bounding Regions)변경 연산에 대해 효율적으로 대처하는 동시성 제어 기법을 제안한다. 분할 시 탐색이 지연되는 시간을 최소화 하기 위해 대부분의 과정에서 질의와 호환되는 공유 래치를 획득한 후 수행하고 분할이 발생된 노드에 엔트리들이 복사되는 동안만 배타 래치를 획득하는 방법을 사용한다. MBR 변경 연산의 동시성을 높이기 위해 부분적인 잠금 결합을 사용한다. 즉, MBR 변경 연산중 주로 발생되는 MBR이 증가되는 삽입연산은 잠금 결합을 수행하지 않고, 감소되는 삭제 연산만 잠금 결합을 수행한다. 또한 성능 평가를 통하여 제안된 동시성 제어 기법이 GiST의 동시성 제어 알고리즘에 비해 처리율 관점에서 성능이 우수함을 보인다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10a
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• pp.30-32
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• 2000

최근 메타데이타의 주요 논쟁점으로 메타데이타의 표준화 문제가 등장하고 있다. 새로운 표준화 방향으로 인한 메타데이타의 확장성은 기존 메타데이타 관리 기법의 변화를 요구하게 되었다. 즉, 사용자의 질의에 대한 신속한 정보 제공과 동적인 자료의 일관성 있는 저장과 유지방 안을 필요로 한다. 이에 본 논문에서는 디지털 라이브러리 환경에서 메타데이타 속성을 정의하고, 이러한 요구사항을 만족하는 병행수행 제어 기법인 2VL(Two Version using the Latch)을 제안한다. 2VL은 래치를 사용하여 2버전을 유지함으로써 판독과 기록 연산간의 충돌로 인한 지연을 최소화하며 판독 연산에 있어서의 빠른 응답시간과 높은 최근성 반영율을 보인다.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.40-41
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• 2006

본 논문은 수직형 트랜치 IGBT 구조에서 에미터를 트랜치로 형성하여 그 전기적인 특성을 MEDICI를 이용하여 고찰하였다. 제안한 구조의 항복전압과 온-상태 전압, 래치업 전류 그리고 턴-오프 시간이 기존 트랜치 IGBT에 비하여 향상되었음을 알 수 있었다. 항복전압은 트랜치 에미터에 의해 트랜치 게이트에 집중되는 전계를 완화시켜 일반적인 트랜치 IGBT보다 19%정도 향상되었으며 온-상태 전압과 래치업 전류는 각각 25%, 16% 정도 향상되었다. 하지만 제안된 구조의 턴-오프 시간은 무시할 수 있을 정도로 약간 증가하였음을 알 수 있었다.

• Journal of IKEEE
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• v.18 no.1
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• pp.25-30
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• 2014

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

• The KIPS Transactions:PartD
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• v.11D no.4
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• pp.809-822
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• 2004

In this paper, we propose a concurrency control algorithm based on R-tree for spatial database management system. The previous proposed algorithms can't prevent problem that search operation is to be blocking during update operations. In case of multidimensional indexes like R-tree, locking of update operations may be locked to several nodes, and splitting of nodes have to lock a splitting node for a long time. Therefore search operations have to waiting a long time until update operations unlock. In this paper we propose new algorithms for lock-free search operation. First, we develop a new technique using a linked-list technique on the node. The linked-list enable lock-free search when search operations search a node. Next, we propose a new technique using a version technique. The version technique enable lock-free search on the node that update operations is to be splitting.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.1
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• pp.25-30
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• 2014

The dynamic characteristics of a gas circuit breaker depend on the underlying high-speed operating mechanism with a spring-actuated latch system. Many studies have been carried out to reduce the breaking time of circuit breakers. In this study, the optimum latch contour design is determined for reducing the breaking time of a circuit breaker. A multi-body dynamic model of the latch is established for analyzing the dynamic behaviors of the circuit breaker by using the MSC/ADAMS program. Simulation results are matched against experimental data. VisualDoc is employed for determining the optimal latch contour. From the optimum design, the breaking time of a gas circuit breaker is improved by about 8.6%.