• Title/Summary/Keyword: 디지털 회로 설계

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미래 지식정보사회의 정보보호 전략 프레임워크

  • Hwang, Jung-Yeon
    • Information and Communications Magazine
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    • v.26 no.1
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    • pp.31-37
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    • 2009
  • 우리나라는 세계 최고 수준의 IT 인프라를 기반으로 네트워크 및 서비스 융합, RFID 등 u-IT 서비스 확산 등을 통해 유비쿼터스 사회로 빠르게 진입하고 있다. 향후 디지털 융합이 가속화됨에 따라 시간과 공간의 제약 없이 원하는 정보의 획득 활용이 증가하고, u-Health, u-learning 등 IT가 타산업과 융합되면서 높은 부가가치를 창출할 것으로 전망 된다. 그러나 정보화의 급속한 진전에 따른 사회 전반의 편의성과 효율성이 향상하였으나, 해킹 바이러스, 개인정보 유출사고, 스팸 등 역기능으로 인한 피해도 확산되고 있다. 최근에는 네트워크 방어체계를 무력화시키는 지능화된 해킹, 대량의 고객정보 유출, 사회공학 기법을 활용한 피싱 등 이용자의 자산과 프라이버시를 침해하는 사이버범죄 증가 등으로 이용자자산과 권리 보호관점에서의 정보보호의 중요성이 부각되고 있다. 향후 시간과 장소에 상관없이 지식정보를 활용하여 편리하고 쾌적한 생활을 누리게 하는 지식정보사회는 예측 불가능한 위험이 곳곳에 산재한 정보위험사회로의 진입을 의미 할 수도 있다. 그러므로 미래사회에서 예상되는 위협을 예측하여 효과적으로 사전에 예방할 수 있는 체계를 마련하는 것은 안전하고 신뢰할 수 있는 지식정보사회를 향유하기 위한 전제조건으로 작용한다. 이에 본고에서는 미래 지식정보사회에 대비한 정보보호 전략으로 안전한 u-사회 청사진 설계 및 환경조성 선도와 국제화, 사이버위협 예방 및 대응체계의 입체적 조화와 융합, 정보보호 기술 제품 산업간 선순환 촉진과 성장 등 3대 전략을 설정하고 실행방안을 제시한다.

A Research on Low-power FFT(Fast Fourier Transform) Design for Multiband OFDM UWB(Ultra Wide Band) Communication System (Multiband OFDM UWB(Ultra Wide Band) 통신시스템을 위한 저전력 FFT(Fast Fourier-Transform) 설계에 관한 연구)

  • Ha, Jong-Ik;Kim, In-Soo;Min, Hyoung-Bok
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.2119.1_2120.1
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    • 2009
  • UWB(Ultra Wide Band)는 차세대 무선통신 기술로 무선 디지털펄스라고도 한다. GHz대의 주파수를 사용하면서도 초당 수천~수백만 회의 저출력 펄스로 이루어진 것이 큰 특징이다[1]. 기존 무선통신 기술의 양대 축인 IEEE 802.11과 블루투스 등에 비해 속도와 전력소모 등에서 월등히 앞서고 있으며, SoC(System on a Chip)의 저전력 구현에 대한 연구가 활발히 진행되고 있다. OFDM은 크게 FFT(Fast Fourier Transform) 블록, Interpolation /decimation 필터 블록, 비터비 블록, 변복조 블록, 등화기 블록 등으로 구성된다. 고속 시스템에서는 대역효율성이 우수한 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 사용하고 있으며, OFDM 전송방식은 직렬로 입력되는 데이터 열을 병렬 데이터 열로 변환한 후에 부반송파에 실어 전송하는 방식이다. 이와 같은 병렬화와 부반송파를 곱하는 동작은 IFFT와 FFT로 구현이 가능한데, FFT 블록의 구현 비용과 전력소모를 줄이는 것이 핵심사항이라고 할 수 있다. 기존논문에서는 OFDM용 FFT 구조로 단일버터플라이연산자 구조, 파이프라인 구조, 병렬구조 등의 여러 구조가 제안되었다[2]. 본 논문에서는 Radix-8 FFT 알고리즘 기반의 New partial Arithmetic 저전력 FFT 구조를 제안하였다. 제안한 New partial Arithmetic 저전력 FFT구조는 곱셈기 대신 병렬 가산기를 이용 하여 지금까지 사용되는 FFT 구조보다 전력소모를 줄일 수 있음을 보였다.

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A Design of Effective Analog-to-Digital Converter Using RC Circuit for Configuration of I2C Slave Chip Address (I2C 슬래이브 칩의 주소 설정을 위한 RC회로를 이용한 효과적인 아날로그-디지털 변환기 설계)

  • Lee, Mu-Jin;Seong, Kwang-Su
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.26 no.6
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    • pp.87-93
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    • 2012
  • In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

Modular Multiplier based on Cellular Automata Over $GF(2^m)$ (셀룰라 오토마타를 이용한 $GF(2^m)$ 상의 곱셈기)

  • 이형목;김현성;전준철;유기영
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.1_2
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    • pp.112-117
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    • 2004
  • In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}+1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.

Precise Time-Synchronization for Separate systems (서로 분리된 시스템의 정밀한 시간동기화)

  • Lee, S.H.
    • Journal of rehabilitation welfare engineering & assistive technology
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    • v.5 no.1
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    • pp.111-115
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    • 2011
  • In this paper, we present a novel time-synchronization method for distributed systems to measure the body motion. The distributed system scheme is considered because human data acquisition systems tend to have a centralized controller with sensors connected with a long range of electric wires running through the subject's body, which results in inconvenience. Utilizing simple key switches and digital input ports for reading the key, the proposed method requires a very simple hardware structure, which means less power consumption compared with the well-known ubiquitous sensor network. After measuring the motion data as well as the synchronization pulses, the proposed method compensates, in offline, the difference of the sampling instance between the two systems by scaling the time difference. The paper presents experimental results to show the validity of the proposed method.

Digital Control Unit Design for Power Amplifier Performance Improvement (전력증폭기 성능개선을 위한 디지털 제어장치 설계)

  • Lee, Byung-Sun;Roh, Hee-Jung
    • 전자공학회논문지 IE
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    • v.47 no.4
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    • pp.34-38
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    • 2010
  • In this paper, we suggest DCU(Digital Control Unit) for performance improvement and stability security of base station power amplifier. The designed DCU controls electric power that is supplied to power amplifier. When the regular input is 10dBm, the regular output is measured 47.8dBm and the results are compared between the case of the applying and the non-applying the DCU. We got the result that PA system is very stable as DCU are very well operating in the boundary degradation of IMD by the over-power level input.

Design and Fabrication of RF evaluation board for 900MHz (900MHz대역 수신기용 RF 특성평가보드의 설계 및 제작)

  • 이규복;박현식
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.3
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    • pp.1-7
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    • 1999
  • A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.

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A Digital Audio Respose System Based on the RELP Algorithm (RELP 방식을 이용한 디지털 음성 응답기)

  • 김상용;은종관
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.6
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    • pp.7-16
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    • 1984
  • This paper describes the overall procedure of the development of a digital audio response system. It has been developed specifically as an answering system to the inquiries of telephone numbers from subscribers. The system has been realized based on the residual excited linear prediction (RELP) algorithm that incorporates a pitch predictive loop. Its major advantage over other similar systems is that it produces high quality of synthetic speech, although its memory size is relatively small. The hardware which consists of a speech synthesizer, a controller and an I/O part has been constructed using 2900 series bit-slice microprocessors and an INTEL 8085 microprocessor. The system is capable of real time processing, reliable, and adaptable to other applications.

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Uniform DFT Polyphase Filterbank based DF Method for Frequency Hopping Signal Direction Finding (주파수 도약신호 방탐을 위한 균등 디지털주파수변환 폴리페이즈 필터뱅크 기반 방탐기술)

  • Lee, Young-Jin;Kwon, Hyuk-Ja
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.3
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    • pp.119-128
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    • 2017
  • In this paper, the wideband direction finding algorithm and system design method for short duration signal such as frequency hopping or burst signal is presented. The polyphase filterbank that it is possible for the near perfect reconstruction was used as a pre-processing and in each subband power measurement was performed to determine whether the presence of a signal and finally general direction finding algorithm was performed. In addition, various experiments was performed using Matlab Simulink and collected data from wideband receiver to verification of the proposed algorithm.

A Study on the Realization of Echo Canceller in CDMA Mobile Communication Networks (CDMA 이동통신 망에서의 반향제거기 구현에 관한 연구)

  • 유태훈;박광철;이윤희;김기두
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.5
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    • pp.36-47
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    • 2000
  • The CDMA digital cellular systems provide better voice Quality than analog systems, however there exists inherent delays due to speech coding and transmission processing, which brings echoes returned by the BSC and PSTN interface. In this paper, we show the performance improvement of a proposed echo canceller by real time implementation, where Block Update NLMS algorithm is applied into the TMS320C54X DSP. By applying the proposed method into the practical mobile phone, we verify that various types of echoes (LE, ESE, AE) may be removed more precisely. We also cope with echo path change resulting from change of delay length after taking VAD to find echo path delay.

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