• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.2
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• pp.51-59
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• 2002

In this paper, we studied the voice cryptograph system designed by the SEED algorithm for the safe transmission and receipt on the voice communication. Voice band signal converts to digital signal by the CODEC and DSP that applied the improved SEED algorithm encrypt the digital signal. The CODEC convert Encryption signal into analog voice signal. This voice signal is transmitted safely because of encryption signal even if someone wiretap. Receiver can hear the source voice, because the encryption signal decrypted using the SEED algorithm. In this paper, We designed the 32 round key instead of 16 round key in the SEED algorithm so that we improve the truncated differential probability from $2^{-143.1}$ to $2^{-286.6}$. 

• 한국벤처창업학회:학술대회논문집
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• 2022.11a
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• pp.79-81
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• 2022

최근 정보기술의 발달과 COVID-19으로 인해, 많은 유통의 판도가 바뀌었다. 비대면의 급증으로 배달문화와 온라인 쇼핑과 온라인 회의 등이 성행하며 익숙해지고 이로 인해 디지털 전환이 더욱 빠르게 가속화 되었다. 중국에서 시작되었던 라이브 커머스도 이 시기를 틈타 한국으로 들어왔고 라이브 커머스의 발전이 시작되었다. 이에 따라 라이브 커머스에 관한 연구도 많이 나오고 있는데 연구들이 라이브커머스의 특성만을 다루는 것에 한계점을 느꼈다. 이에 본 연구는 라이브 커머스의 특성에서 나아가 이 특성으로 인하여 진정으로 혜택을 볼 수 있는 소상공인들에 초점을 맞추기로 하였다. 소상공인들이야말로 라이브커머스를 이용하는 80%를 넘는 비중을 차지하고 있는 사용자이자 판매자이다. 하지만 그럼에도 불구하고 아직까지도 많은 판매자들이 라이브커머스를 어렵게 생각하고 전문 방송인을 고용하거나 대행사를 고용하여야만 라이브커머스 방송이 가능하다고 생각하여 시작을 못하고 있다. 본 연구에서는 실험을 설계하여 판매자가 직접 라이브 커머스 방송을 진행하여도 충분히 소비자에게 긍정적인 영향을 줄 수 있고 매출액과 유입수에도 영향을 끼칠 것이란 가설을 설정하였다. 쇼호스트와 관여도라는 변수를 설정하여 2 by 2 실험을 설계하였다. 쇼호스트는 방송전문가인 일반적인 대행사를 섭외하여 방송을 능숙하게 하고 중간에 재미적인 요소를 집어 넣는 쇼호스트와 제품 전문가인 판매자를 직접 방송하게 하여 제품에 대한 전문성을 넣어 소비자의 반응을 살펴 보았다. 관여도는 고관여 제품과 저관여 제품을 식품군으로 비교하는 것으로 설계하는 것으로 연구를 진행하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.1
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• pp.41-54
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• 2004

In this paper, we propose a new digital hearing aid circuit that compensates the impaired threshold level changing nonlinearly using a multi-band compensation technique. In the algorithm the hearing frequency range 8kHz is divided into 64 bands which is 125Hz resolution. Each band is controlled finely to compensate the hearing impaired proportional to personal ROM table. The multi-band is introduced using a FFT/IFFT Processor which makes to control in frequency domain. As a result, the proposed circuit is more efficient $15\%$ than a conventional ones such as FIR filter architecture in terms of the compensation gun and accuracy. The hardware size was reduced $65\%$ than a general FFT by pre-handling of the input data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.1-7
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• 2007

An MTJ element not only computes Boolean function but also stores the output result in itself. We can make the most use of magneto-logic's merits by employing the magneto-logic in substitution for the sequential logic as well as the combinational logic. This unique feature opens a new horizon for potential application of MTJ as a universal logic element. Magneto-logic circuits using MTJ elements are more integrative and non-volatile. This paper presents novel 3-bit magneto-logic up/down counters and presents simulation results based on the HSPICE macro-model of MTJ that we have developed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.30-38
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• 2003

UDP library of Verilog HDL has been used for simulation of digital systems. But it takes a lot of time and efforts to generate a gate-level library equivalent to the UDP library manually due to the characteristic of UDP that does not support synthesis. It is indispensable to generate equivalent gate-level model in testing the digital systems because fault coverage can be reduced without the equivalent gate-level models. So, it is needed to automate the process of generating the equivalent gate-level models. An algorithm to solve this problem has been proposed, but it is unnecessarily complex and time-consuming. This paper suggests a new improved algorithm to implement the conversion to gate-level models, which exploits the characteristic of UDP Experimental results are demonstrated to show the effectiveness of the new algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.27-35
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• 2004

Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.1001-1008
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• 1991

.In this paper the efficient clock recovery algorithm is proposed to regenerate the manchester code at the system using the Manchester encoding scheme such as LAN. Mobile communication and digital communication systems. The proposed clock recovery circuit recovers the clock using the two times of the same original transmitted frequency can be completely recovered. The implementation of the proposed clock recovery circuit and the interpretation of test results prove the validity of the proposed algorithm.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.590-605
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• 2014

The purpose of this paper is to propose a service system for a digital hologram video, which has not been published yet. This system assumes the existing service framework for 2-dimensional or 3-dimensional image/video, which includes data acquisition, processing, transmission, reception, and reconstruction. This system includes acquisition of color and depth image pairs from a image acquisition system with vertical rigs, rectification of acquired image pairs and generating digital hologram. Also it is designed to reduce the CGH (computer-generated hologram) generation time to 1/3. It also includes some additional and optional functions such as watermarking, compression, and encryption.