• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.29 no.1
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• pp.133-139
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• 2005

Resonant-Type Magnetometer(RM) using high permeability isotropic magnetic material is designed to implement Smart Digital Compass. Theoretically, the inductance L of a coil, winding on the magnetic core, is proportion to the change of permeability $\mu(H)$ and, the change values of L can be obtain as the change of frequency by simple Schmitt Trigger circuit. By the use of integrated circuit switch, the RM can be designed with simple circuit and it can provide overcoming the drift by temperature and the variation of operating points in $\mu(H)$ curve. The facts that Metglas 2705M is an optimum magnetic material and ship's permanent magnetism can be obtain from measured values of RM are also known in this study.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.158-164
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• 2002

2-6 GHz digital phase shifter module has been designed and fabricated. For the broadband operation and performance, MMIC phase shifter chip for phase shifter module was designed and fabricated by using the reflection-type circuits with Lange coupler. The fabricated phase shifter module shows 6.1$^{\circ}$RMS phase error, 13.5 dB maximum insertion loss, and 8 dB and 10 dB input and output return losses, respectively. Computer controlled measurement systems are realized in order to get the measured data of 32 phase states. The RMS insertion phase error and the average insertion loss deviation among 8${\times}$8 modules for the phased-array system are less than ${\pm}$0.5$^{\circ}$and ${\pm}$0.5 dB, respectively. The size of fabricated phase shifter module is 45 ${\times}$ 22.5 ${\times}$60㎣.

• Journal of Digital Convergence
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• v.13 no.12
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• pp.391-400
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• 2015

This research analyzes the actual condition and trend in 119 research papers about sadness mediation program for senior citizens, which were published from 1990 to 2014, to find an expansive way for seniors. And the result is as in the following: publish year of subjects is 2010 to 2014, research plan was done by experimental-control group plan, and we quoted the most of the yardstick from foreign research, in the case of the seniors stays in their own house. Art therapy is the most common way of mediation, and most programs were done less than 10 times, once in a week, and less than 60 minutes in once. And variable of efficacy is verified in the order of physical ability, self-worth, and cognitive function. As the first research that analyzes the trend of sadness mediation program for senior citizens, this research is expected to help setting the direction of future research. that is related to convergence.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.585-588
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• 2014

This paper presents a self-powered sensor node circuit using photovoltaic and vibration energy harvesting. The harvested energy from a solar cell and a vibration device(PZT) is stored in a storage capacitor. The stored energy is managed by a PMU(Power Management Unit). In order to supply a stable voltage to the sensor node, an LDO(Low Drop Out Regulator) is used. The LDO drives a temperature sensor and a SAR ADC(Successive Approximate Register Analog-to-Digital Converter), and 10-bit digital output data corresponding to current temperature is obtained. The proposed circuit is designed in a 0.35um CMOS process, and the designed chip size including PADs is $1.1mm{\times}0.95mm$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.208-214
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• 2003

Because the digital control includes microprocessor different from an analog control, the digital control enables to monitor internal parameters of DC-DC converter and to control output voltage remotely by communicating with a Window based PC and also to monitor whether exact voltage is output or not. These things are impossible in an analog control. In this paper, a simple buck converter controlled by DSP(TMS320C31) is implemented. This converter outputs 0V to 5V from 15V input voltage and is controlled by a PD algorithm using DSP. Finally the response characteristics of a step reference voltage and in a steady state are analyzed to verify the usefulness of this digital controlled converter.

• Journal of Broadcast Engineering
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• v.8 no.3
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• pp.228-237
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• 2003

Eureka-147 DAB(Digital Audio Broadcasting) system on which DMB(Digital Multimedia Broadcasting) system is based, was designed for the requirements of CD qualify audio with ${10}^{-4}$ bit error rate. Audio program may be primary service in DAB system, but multimedia program can be primary service in DMB system. Therefore, the bit error rate required must be below ${10}^{-7}$∼${10}^{-8}$ to transmit multimedia data via DMB channel. In order to meet the requirements and keep backward compatibility of DAB system we propose an outer channel coding scheme using Reed-Solomon coding and convolutional interleaving. This paper shows the simulation results for DMB channel performance based on mobile channel model. Also, it describes the needs and the effects of the outer channel coding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.