• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.2
• /
• pp.88-95
• /
• 1999

Stack filters are a class of digital nonlinear filters with excellent properties for signal restoration. Unfortunately, present algorithms for designing stack filters with large window size are limited in applications by their computational overhead and serial nature. In this paper, new, highly-parallel algorithm is developed for determining a stack filter which minimizes the mean absolute error criterion. It retains the iterative nature of the present adaptive algorithm, but significantly reduces the number of required to converge to an optima filter. A proof is also give that the proposed algorithm converges to an optimal stack filter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.11
• /
• pp.85-95
• /
• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.3
• /
• pp.531-536
• /
• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.79-85
• /
• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2003.05b
• /
• pp.1477-1480
• /
• 2003

본 논문에서는 실시간 데이터 및 보안데이터, 영상데이터 통을 전송할 때 잡음으로 인해 발생되는 데이터 오류를 효과적으로 복원하기 위해 오류 정정 능력이 뛰어난 터보코드를 적응하여 신뢰성 있는 영상전송 시스템을 실현하였다. 영상처리 시스템에서는 CCTV, 비디오 카메라 등에서 나오는 NTSC(National Television System Committee) 영상 신호를 비디오 디코더를 통해 A/D 변환하여 출력하였다. 변환된 디지털 영상정보는 두 개의 영상필드로 출력되며 그중 하나의 필드가 선택되는 알고리즘을 EPLD(Erasable Programmable Logic Device) 로직회로로 구성하여 디지털 영상 데이터를 절반으로 줄이는 시스템을 구현하였다. 터보코드의 부호기, 복호기 시스템에서는 실수연산이 가능한 DSP(Digital Signal Processor)를 사용하여 터보코드를 구현하였으며, 터보코드의 성능을 좌우하는 인터리버부분은 블록 인터리버를 적용하여 설계하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.443-447
• /
• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.7B
• /
• pp.1081-1090
• /
• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• Journal of Korean Library and Information Science Society
• /
• v.50 no.4
• /
• pp.469-491
• /
• 2019

The purpose of the study is to establish a plan for the development of digital person archives with the case of Geum-nam Kim, the third-generation head of the Christian Donggwangwon Monastery Society. The step-by-step strategy for building digital character archives for Geum-nam Kim is as follows. 1)The reason and expected effect of the character selection are analyzed. Since he was a survivor, he has recorded and typed his life history through several interviews. Considering that the memory of Geum-nam Kim, who is over 90 years old, could be mixed up in the time of the incident, the advice of Sister Donggwangwon and Maj. Gen. Gyuillwon, the lower unit of Donggwangwon, was obtained and verified for accuracy. 2)The contents of the records and the place of collection were identified, and the total content composition(proposal) was presented by reclassifying and relocating the records identified records. The entire contents are divided into recorded contents and explanatory contents, so that they can be linked to each area and collection.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.3
• /
• pp.188-198
• /
• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.10a
• /
• pp.1027-1030
• /
• 2015

하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.