• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.5
• /
• pp.358-368
• /
• 2020

Grid-connected inverters (GCIs) based on renewable energy sources play an important role in enhancing the sustainability of a society. Harmonic standards, such as IEEE 519 and P1547, which require the total harmonic distortion (THD) of the output current to be less than 5%, should be satisfied when GCIs are connected to a grid. However, achieving a current THD of less than 5% is difficult for GCIs with an output filter under a distorted grid condition. In this study, a novel harmonic compensation method that uses a digital lock-in amplifier (DLA) is proposed to eliminate harmonics effectively at the output of GCIs. Accurate information regarding harmonics can be obtained due to the outstanding performance of DLA, and such information is used to eliminate harmonics with a simple proportional-integral controller in a feedforward manner. The validity of the proposed method is verified through experiments with a 5 kW single-phase GCI connected to a real grid.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.8
• /
• pp.67-74
• /
• 2004

In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track ＆ Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

• Proceedings of the KIPE Conference
• /
• 2018.11a
• /
• pp.104-106
• /
• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.5
• /
• pp.51-58
• /
• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of IKEEE
• /
• v.2 no.1 s.2
• /
• pp.34-41
• /
• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.52-57
• /
• 2011

This paper presents a 4-channel optical transmitter circuit realized in a $0.18{\mu}m$ CMOS technology for high-speed digital interface. Particularly, the VCSEL driver exploits the feed-forward technique, and the pre-amplifier employs the pulse-width control. Thus, the optical transmitter operates at the bias current up to 4mA and the modulation current from $2{\sim}8mA_{pp}$. with the pulse-width distortion compensated effectively. The 4-channel optical transmitter array chip occupies the area of $1.0{\times}1.7mm^2$ and dissipates 35mW per channel at maximum current operations from a single 1.8V supply.

• Proceedings of the KIPE Conference
• /
• 2018.11a
• /
• pp.95-97
• /
• 2018

The power quality of Single Phase Grid-Connected Inverters (GCIs) has received much attention with the increasing number of Distributed Generation (DG) systems. However, the performance of single phase GCIs get degraded due to several factors such as the grid voltage harmonics, the dead time effect, and the turn ON/OFF of the switches, which causes the harmonics at the output of GCIs. Therefore, it is not easy to satisfy the harmonic standards such as IEEE 519 and P1547 without the help of harmonic compensator. To meet the harmonic standards a certain kind of harmonic controller needs to be added to the current control loop to effectively mitigate the low order harmonics. In this paper, the harmonic compensation is performed using a novel robust harmonic compensation method based on Digital Lock-in Amplifier (DLA). In the proposed technique, DLAs are used to extract the amplitude and phase information of the harmonics from the output current and compensate it by using a simple PI controller in the feedforward manner. In order to show the superior performance of the proposed harmonic compensation technique, it is compared with those of conventional harmonic compensation methods in terms of the effectiveness of harmonic elimination, complexity, and implementation. The validity of the proposed harmonic compensation techniques for the single phase GCIs is verified through the experimental results with a 5kW single phase GCI. Index Terms -Single Phase Grid Connected Inverter (SPGCI), Harmonic Compensation Method, Total Harmonic Distortion (THD) and Harmonic Standard.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.156-167
• /
• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.25-33
• /
• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.9
• /
• pp.1847-1855
• /
• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.