• Title/Summary/Keyword: 디지털 변조방식

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Image Quality Evaluation of Digital X-Ray Detector Using Amorphous Selenium Layer and Amorphous Silicon TFT Array (비정질 셀레늄층과 비정질 실리콘TFT배열을 사용하는 디지털 X-선 검출기의 영상특성 평가)

  • Kim, Chang-Won;Yoon, Jeong-Key;Kim, Jong-Hyo
    • Progress in Medical Physics
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    • v.19 no.4
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    • pp.219-226
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    • 2008
  • In this study, we have conducted characterization of imaging performance for a flat panel digital X-ray detector using amorphous Selenium and a-Si TFT which was developed by the authors. The procedures for characterization were in concordance with internationally recommended standards such as IEC (international electrotechnical commission). The measures used for imaging performance characterization include response characteristic, modulation transfer function (MTF), detective quantum efficiency (DQE), noise power spectrum (NPS), and quantum limited performance. The measured DQEs at lowest and highest spatial frequencies were 40% and 25% respectively, which was superior to that of commercial products by overseas vendor. The MTF values were significantly superior to that of CR and indirect type DRs. The quantum limited performance showed the detector was limited by quantum noise at the entrance exposure level below 0.023 mR, which is sufficiently low for general X-ray examination.

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3rd SDM with FDPA Technique to Improve the Input Range (입력 범위를 개선한 FDPA 방식의 3차 시그마-델타 변조기)

  • Kwon, Ik-Jun;Kim, Jae-Bung;Cho, Seong-Ik
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.192-197
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    • 2014
  • In this paper, $3^{rd}$ SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input range is proposed. Conventional architecture with $3^{rd}$ transfer function is just made as adding a digital delay path in $2^{nd}$ SDM architecture. But the input range is very small because feedback path into the first integrator is increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so input range could be improved about 9dB. The $3^{rd}$ SC SDM with only one operational amplifier was implemented using double-sampling technique. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of $700{\mu}W$ and Dynamic Range of 82.8dB.

A Study on the Design and Implementation of FH Frequency Synthesizer for GSM Mobile Communication (GSM 이동통신을 위한 FH 주파수 합성기 설계 및 구현에 관한 연구)

  • 이장호;박영철;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.2
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    • pp.168-180
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    • 1992
  • Commumication technology has been continuously developed to overcome the distance and time for the transmission of information to the human society. Wireless mobile communication, which had been used mostly in the military and police is widely used these days for enterprise and individuals. Therefore the domestic usage of the advanced mobile phone service are progressively gaining wide popularity. The modulation techniques used usually in mobile communications were the analog techniques such as AM and FM, but they are getting replaced by the digital techniques, However, the major disadvantage of the digital communications is the increase of the transmission bandwidth. Therefore, it is very important to use efficiently the limited frequency bandwidth. The domestic research and development on the subject seems quite limited and in order to establish the technology of the digital mobile communications. This thesis presents the design of the frequency hopping synthesizer providing 124 channels with a channel spcing of 200KHz. VCD used in the synthesizer employs a semi-rigid cable for higher purity of signal spectrum, and a hybrid pgase detector is realized with a sample hold phase detector in conjuction with a tri-state phase detedctor.

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The Design of the Class E Swiching Frequency Multiplier (스위칭 모드 E급 주파수 체배기 설계)

  • Roh, Hee-Jung;Seo, Choon-Weon
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.10
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    • pp.90-99
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    • 2009
  • In this paper, we proposed the new class-E frequency multiplier design that include the highest efficient characteristics. The proposed frequency multiplier is designed for 5.8[GHz] output using the frequency multiplier about 2.9[GHz] input signal. And studying in this paper is for the design and the implementation of the class E frequency multiplier. For the result, the maximum highest efficient characteristics 32[%] which is with output power 24.5[dBm] and 8.5[dB], is shown with frequency multiplier for the 2.9/5.8[GHz] class E. And we applied the linear method to the implemented class E frequency multiplier. As a result, the output spectrum for the linear is upgrade to 12[dB], 12[dB], 13[dB] of the ACPR characteristics on the +11[MHz], +20[MHz], +30[MHz] offset frequency in the center frequency. The result is satisfied with the 3.83[%] of the lineared EVM for the 64-QAM modulated method with the 54[Mbps] transmission velocity. In this paper, we show that the good compensation result of the linearity and the efficiency through the digital pre-linear method of the distortion with the frequency multiplier. Therefore, we suggested the frequency multiplier method are applying to WLAN, cellular, PCS, WCDMA, and etc.

Development of a Multichannel Eddy Current Testing Instrument(I) (다중채널 와전류탐상검사 장치 개발(I))

  • Lee, Hee-Jong;Nam, Min-Woo;Cho, Chan-Hee;Yoon, Byung-Sik;Cho, Hyun-Joon
    • Journal of the Korean Society for Nondestructive Testing
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    • v.30 no.2
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    • pp.155-161
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    • 2010
  • Recently, the electromagnetic techniques of the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In this study, the synthesizer module and the analog module which are essential to the ECT system were primarily developed. The developed ECT system is basically a multifrequency type which is able to inject the maximum four frequencies based on the frequency and time domain multiplexing method. Conclusively, we confirmed that the EC signal was processed appropriately in each circuit modules, and the Lissajous EC signal was displayed in the impedance plane.

Hardware Design of SNR Estimator for Adaptive Satellite Transmission System (적응형 위성 전송 시스템을 위한 신호 대 잡음비 추정 회로 구현)

  • Lee, Jae-Ung;Kim, Soo-Seong;Park, Eun-Woo;Im, Chae-Yong;Yeo, Sung-Moon;Kim, Soo-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.2A
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    • pp.148-158
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    • 2008
  • This paper proposes an efficient signal to noise ratio (SNR) estimation algorithm and its hardware implementation for adaptive transmission system using M-ary modulation scheme. In this paper, we present the implementation results of the proposed algorithm for the second generation digital video broadcasting via satellite (DVB-S2) system, and the proposed algorithm can be tailored to the other communication systems using adaptive transmissions. We built a look-up table (LUT) using the theoretical background of the received signal distribution, and by using this LUT we need just two comparators and a counter for the hardware implementation. For this reason, the hardware of the proposed scheme produces accurate estimation results even with extremely low complexity. The simulation results investigated in this paper reveal that the proposed method can produce estimation results within the specified SNR range in the DVB-S2 system, and it requires a few hundreds of samples for average estimation error of about 1 dB.

Asymmetric public-key watermarking based on correlation method (상관도 검출기반의 비대칭 공개 키 워터마킹)

  • Li De;Kim Jong-Weon;Choi Jong-Uk
    • Journal of the Korea Society of Computer and Information
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    • v.10 no.3 s.35
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    • pp.151-159
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    • 2005
  • Traditional watermarking technologies are symmetric method which embedding and detection keys are same. Although the symmetric watermarking method is easy to detect the watermark, this method has weakness against to malicious attacks to remove or modify the watermark information when the symmetric key is disclosure. Recently, the asymmetric watermarking method that has different keys to embed and detect is watched several researchers as a next generation watermarking technology. In this paper, we have expanded search space of secret key using the solution set of linear simultaneous equations. Secret key is generated by secure linear transformation method to prevent of guessing secret key from public key, and the correlation value between secret key and public key is high. At theresults, the multi bits information can be embedded and high correlation value was detected after JPEG compression.

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Secure Asymmetric Watermarking Based on Correlation Detection (상관도 검출기반의 안전한 비대칭 워터마킹)

  • Li De;Kim JongWeon;Choi JongUk
    • The KIPS Transactions:PartC
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    • v.12C no.3 s.99
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    • pp.379-386
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    • 2005
  • Traditional watermarking technologies are symmetric method which embedding and detection keys are same. Although the symmetric watermarking method is easy to detect the watermark, has method has weakness against to malicious attacks to remove or modify the watermark information when the symmetric key is disclosure. Recently, the asymmetric watermarking method that has different keys to embed and detect is watched several researchers as a next generation watermarking technology. In this paper, we have expanded search space of secret key using the solution set of linear simultaneous equations. Secret key is generated by secure linear transformation method to prevent of guessing secret key from public key, and the correlation value between secret key and public key is high. At the results, the multi bits information can be embedded and high correlation value was detected after JPEG compression.

A Study on the Development of SSB Modem (디지털 SSB 모뎀 개발에 관한 연구)

  • Jin, Heung-Du;Choi, Jo-Cheon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.693-697
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    • 2007
  • The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication, but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$ delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s$, $130{\mu}s$, $200{\mu}s$ delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s$, $160{\mu}s$, $250{\mu}s$ delay time at 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the German PACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.

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A Study on the Development of SSB Modem (디지털 SSB 모뎀 개발에 관한 연구)

  • Kim, Jeong-Nyun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.10
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    • pp.1852-1857
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    • 2007
  • The SSB modem performs the modulation process which converts the digital voltage level to the audible frequency band signal and the demodulation process which converts reversely the audible frequency signal to the digital voltage level. The modulator and the demodulator are implemented with a single DSP chip. Because of the SSB specific character, the distortion occurs when the frequency is changed. This distortion has no effect on voice communication but it has an significant effect on data communication. In other words, it is impossible to send data stream with adjacent 2 periods. Therefore, in case of using 2-tone FSK, it is needed to send at least 3 periods to transmit 1 bit. Therefore we implemented the modem using modified phase-delay shift keying to transmit 1 tone signal for high speed transmission. In the 1200[bps] mode, it generates 0, $187{\mu}s$, delay time at 1.3kHz symbol frequency, and in the 2400[bps] mode, 0, $70{\mu}s\;130{\mu}s\;200{\mu}s$, delay time at 1.5kHz symbol frequency. Finally, in the maximum 3600[bps] mode, it generates 0, $100{\mu}s\;160{\mu}s\;250{\mu}s$ 2.0kHz symbol frequency. The measured results of the implemented SSB modem shows a good transfer functional characteristic by spectrum analyzer, almost same bandwidth in pass band and 20dB higher SNR comparing the emu FACTOR and American CLOVER and in the experimental transmitting test, we verified the transmitted data is received correctly in platform.