• The Journal of the Acoustical Society of Korea
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• v.24 no.7
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• pp.387-394
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• 2005

In this paper, we propose a new transmission technique of audio signals for the serial connection of the speakers of multiple-channel audio systems. Analog audio signals from a multi-channel audio system are converted into digital signals with signal processing steps and transferred to each speaker through a serial line. The signal processing steps contain data compression and packet generation in association with audio signal characteristics. Each speaker gets its corresponding digital audio signals from the transmitted packets and converts the signals into analog audio signals to make sounds with the speaker All the proposed functions in this paper are modeled in VHDL. implemented with FPGA chips, and tested for actual multi-channel audio systems.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.9-12
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• 2010

This paper presents design and implementation of infrared thermal image processing system based on the digital media processor for disaster monitoring. The digital thermal image processing board is designed and implemented by using commercial chips such as DM642 processor and video encoder, video decoder. The implemented functions for disaster monitoring are to analyze temperature distribution of a monitoring infrared thermal image and to detect disaster situation such as fire. For the input of infrared thermal image processing system, an infrared camera of type of the $320\;{\times}\;240\;{\mu}$-bolometer is used. The required functions are confirmed with 10 frame/second of processing performance by testing of the prototype and Practicality of the system was verified.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2006.06a
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• pp.105-108
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• 2006

무선인지(RFID)시스템은 많은 산업 분야에 적용되고 있다. 대표적인 예로써 RFID 시스템을 이용한 출입 관제시스템을 들 수 있으며, 이런 경우 기존의 건물에 이 시스템을 설치하려고 하면 출입문을 개조하여야 한다. 하지만 무선 통신을 이용하면, 리더기에서 호스트 컴퓨터로의 접근이 용이해지므로 출입문 개조에 있어서도 한결 수월해진다. 이 때 필요한 것이 무선 디지털 데이터 통신 기술과 원격지에서 Tag의 ID를 모니터링을 위한 TCP/IP를 이용한 Ethernet 통신이다. 본 논문에서는 이러한 시스템의 개발방법에 대해 설명하였으며 RFID 리더기는 125KHz를 사용 주파수로 하고, Tag 칩은 Microchip사의 MCRF 250을 사용하였다. 그리고 무선 데이터 통신을 위해서 CC1020칩을 사용하였으며 이 칩의 장점은 간단히 레지스터를 설정으로 송신 상태 혹은 수신 상태로 변환이 가능하고 또한 주파수 설정도 가능하다는 것이다. 마지막으로 Ethernet 통신을 위해서는 W3100A칩을 이용하였으며, Ethernet 통신에 있어 OS가 차지하는 부분으로 하드웨어를 통해 구현하였다. 실험을 위해 하드웨어를 구성하고 각 모듈별 동작을 분석하고. 각 부분의 파형을 확인하였다. DB에 해당하는 Application을 통해 Tag ID DATA를 확인하였다.

• Information and Communications Magazine
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• v.9 no.9
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• pp.72-85
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• 1992

The throughput requirement for many digital signal processing is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of function units. The research on a very high throughput VLSI architecture for digital signal processing applications requires the development of an algorithm, decomposition scheme which can minimize data communication requirements as well as minimize computational complexity. The objectives of the research are to investigate computationally efficient algorithms for solution of the class of problems which can be modeled as DLSI systems or adaptive system, and develop VLSI architectures and associated multiprocessor systems which can be used to implement these algorithms in real-time. A new VLSI architecture for real-time 2-D digital signal processing applications is proposed in this research. This VLSI architecture extends the concept of having a single processing units in a chip. Because this VLSI architecture has the advantage that the complexity and the number of computations per input does not increase as the size of the input data in increased, it can process very large 2-D date in near real-time.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.69-79
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• 1999

The research and implementation was preformed on high-resolution CCTV camera with CCD exclusive DSP conventional analog signal processor CCTV camera has its limit on auto exposure(AE), auto white balance(AWB), back light compensation(BLC) processing, severe distortion and noise of image, manual control parameter setting, etc. In our study, to resolve the problems in conventional CCTV camera, we made it possible to control AE, AWB, BLC automatically by the use of the DSP, which are used exclusively in the CCD camera produced domestically, and the microcontroller. And we utilized the function of screen display of microcontroller for the user-friendly interface to control CCD camera. And the electronic variable resister(EVR) was used to avoid setting parameters manually in the level of manufacturing process. As the result, It became possible to control parameters of the camera by program. And the cost-down effect was accomplished by improving the reliability of parameter values and reducing the efforts in setting parameters.

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.91-97
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• 2004

A digital over-sampling noise-shaping coder to achieve the processing accuracy for the audio signal bandwidth is designed. In order to implement an optimized design of the noise-shaping coder as a form of U (intellectual property), circuit design techniques that optimize the multiplication and the ROM architectures are proposed with emphasis on the low-voltage operation under 2.0 V and the minimization of the hardware resources. In the design and verification methodology, the overall architectures and the internal bit width have been determined through behavioral simulations. The overall performances including timing margin have been estimated through transistor-level simulations. Furthermore, the test results of the implemented chip using a 0.35-${\mu}{\textrm}{m}$ standard CMOS process proposed the validity of the proposed circuits and the design methodology.

• Electronics and Telecommunications Trends
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• v.27 no.1
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• pp.93-100
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• 2012

디지털 영상 미디어 기술의 발전과 초고속 무선 전송에 대한 요구가 증가함에 따라 수 Gbps급 무선 전송을 현실화한 연구 결과가 국내외에서 많이 발표되고 있다. 이 가운데 가장 주목을 받고 있는 기술이 바로 60GHz 대역 통신이다. 이는 60GHz 대역이 ISM 대역임에도 불구하고 최대 9GHz까지의 엄청난 대역폭을 활용할 수 있어서 Gbps급 무선 전송에 가장 적합하기 때문이다. 하지만 60GHz 전파는 대기 중 감쇄가 심하기 때문에 무선 네트워크 구성을 위해서는 고성능의 무선 송수신 단말을 필요로 한다. 따라서 단말에서 사용하게 될 안테나 및 송수신 칩은 60GHz 대역의 광대역 신호를 처리하고 고출력, 고이득이 구현되어야 할 뿐만 아니라, 크기, 소모 전력, 그리고 가격적인 측면을 고려해야 하는 고도의 설계 기술을 필요로 하고 있다. 본고에서는 60GHz 대역의 이용 현황, 표준화 동향과 함께 송수신 칩 기술동향에 대해 살펴보고자 한다.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.184-188
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• 2006

This paper presents DSP based narrow band satellite communication signal power detector for tracking control of mobile satellite antenna system. An analog filter based conventional power detector has poor performance due to frequency drift of carrier. Also, it is very difficult to change an analog filter bandwidth according to changed bandwidth of transmitted signal. To solve these difficulties, we proposed DSP based signal power detector, which is easy to change bandwidth of filter and to match shifted frequency of carrier. The proposed signal power detector consists of a FFT function to measure frequency drift of carrier, a programmable filter bank function to limit of received signal bandwidth and a power calculation function to measure power of filtered signal in 12-bit linear scale. Test results of implemented signal power detector, based on TMS320C5402 DSP, showed that it satisfied required functions and performances and properly operated.