• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1175-1178
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• 2007

빠르게 변화하고 있는 모바일 시장에서 개발자들이 응용프로그램 개발을 하면서 가장 자주 사용하고 필요로 하는 것 중 하나가 디버깅이다. 본 논문에서는 기존의 하드웨어 디버거를 통해 ELF 디버깅 정보를 얻어오는 방법 대신 하드웨어 없이 ELF 파일에 대한 정보를 분석하는 툴 구현을 제안한다. ELF 파일을 분석하고 그 정보를 바탕으로 실제 모바일 폰에서 덤프 해온 메모리 값을 보여줌으로써 디버깅을 용이하게 한다. 소프트웨어만으로 디버깅 정보 추출이 가능하므로 고가의 디버깅 장비의 비용 절감의 효과를 가져다 줄 수 있을 것으로 기대된다.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.1
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• pp.1-7
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• 2010

Detecting data races is important for debugging programs with OpenMP directives, because races result in unintended non-deterministic executions of the program. It is especially important to detect the first data races to occur for effective debugging, because the removal of such races may make other affected races disappear or appear. The previous tools for race detecting can not guarantee that detected races are the first races to occur. This paper suggests a tool what detects the first races to occur on the program with nested parallelism using the two-pass on-the-fly technique. To show functionality of this tool, we empirically compare with the previous tools using a set of the synthetic programs with OpenMP directives.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.272-275
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• 2006

C/C++언어로 구현된 응용프로그램들은 언어적인 특성으로 메모리 릭에 취약하다고 알려져왔다. 이에 이러한 언어적인 약점을 보완하기위해 가비지 컬렉션 등과 같은 기술이 연구/발표되어왔다. 그러나 릭이 실제 응용프로그램 사이에서 얼마나 발생이 되고 있으며 얼마나 심각한지 발표된 자료는 찾을 수 없었다. 제안된 보완기술들 조차 실제 응용프로그램을 적용하여 테스트한 사례는 찾을 수 없었다. 따라서, 본 논문에서는 실제 응용 프로그램을 선정하여 메모리 릭의 발생 정도를 측정하고, 발생 원인은 무엇이고 C/C++ 언어간의 릭 발생 특징은 존재하는지 조사해 보고자 한다. 또한 Valgrind 툴을 이용하면서 발견된 문제점을 토론함으로써 향후 더 우수한 동적 메모리 디버깅 툴을 개발하는데 기여하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.355-357
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• 2004

Java의 경우 기존의 강건성 테스팅 방법인 ballista로는 객체 타입의 인자 및 파일 시스템의 변화를 시뮬레이션 할 수 없다. 따라서 객체에 대한 특별한 접근을 필요로 한다. 본 논문에서는 객체에 폴트를 삽입하는 방식을 통하여 자바 가상 기계의 강건성(Robustness)을 테스팅하는 방법을 제안한다. 자바 디버깅 툴인 JPDA를 사용하여 자바 가상 머신에 대한 직접적인 접근 및 의도한 상태 및 환경 변경을 가능하게 하고 이를 통해 자바 가상 기계에 폴트가 심어진 객체를 수행시킬 수 있다. 객체를 수행시키고 의도한 예외상황의 발생 유무를 관찰함으로써 자바 가상 기계의 강건성을 테스트 할 수 있다.

• The KIPS Transactions:PartD
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• v.9D no.1
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• pp.153-160
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• 2002

This paper describes the design and implementation of library for real-time operating system Q+, that was developed for the internet appliance. The library in the real-time operating system should be defined according to the standard interface and support the functions that are adequate to the real-time application. To ensure the compatibility between application programs, the Q+ library follows industrial and international standards, such as POSIX.1, ISO 7942 GKS. And, to support the Q+ application, library provides C standard functions, graphic/window functions, network functions, security support functions, file system functions. The Q+ library was implemented using the Q+ kernel, Digital TV set-top box, and KBUG debugging tool.

• Convergence Security Journal
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• v.22 no.1
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• pp.3-9
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• 2022

The role of the integrated development environment is very important in software development of a development project. After many developers develop different modules, software product is completed through compile, debugging, integration, testing, and distribution. However, bugs and various issues in the development process cause problems such as quality deterioration of software product and dissatisfaction with requirements. So the need for automated testing to avoid these problems and improve quality has increased. In this study, we propose test automation modules of four perspectives to improve quality throughout the test automation in an integrated development environment. Each automation module operates through the tool chain of an integrated build framework implemented on the devops.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.50-56
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• 2011

During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification. SWT/KARI developed the software-based spacecraft simulator based on TSIM-ERC32 processor emulator from Aeroflex Gaisler. But when developing flight software using TSIM-ERC32, there are much limitation for understanding of exact behavior of ERC32 processor, and it is impossible to change or modify the emulator core to develop the satellite simulator. To reslove this problem, this paper presents the development of new cycle-true ERC32 emulator as laysim-erc32 and describes the software development and debugging method on VxWorks/RTEMS RTOS.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.261-265
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• 2005

This paper describes the DC-DC Converter for Ancillary Power Supply in Hybrid Electric Vehicle. DC-DC Converter is used for charging 12V auxiliary battery supplying electric power to head ramp, audio, ECU etc in automobiles. used DC-DC Converter Topology is PS-ZVS FB(Phase Shifted Zero Voltage Switching Full-Bridge) to reduce switching loss and EMI noise induced by high frequency operating condition. And For easy compensation and stable system response characteristic, current mode control method including slope compensation is employed. Constant current / constant voltage charging control method guarantee stable electric charging of auxiliary battery. Simulation toll PSIM6.0 is used for initial circuit parameter settings and H/W debuging. Thermal problems of Switching components in DC-DC Converter is improved by using Thermo Tracer.

• Aerospace Engineering and Technology
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• v.10 no.2
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• pp.105-113
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• 2011

During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification, which can be substituted for the actual hardware. LEO satellites being developed by KARI recently use the MCM-ERC32SC processor for on-board computer (OBC). For the flight software (FSW) development and testing, the software-based spacecraft simulator was developed using TSIM-ERC32 processor emulator from Aeroflex Gaisler. It is needed to get rid of the constraints and dependencies of TSIM-ERC32 processor emulator and to obtain high performance processor emulator to develop full satellite simulator. This paper presents the development of the ERC32 emulator based on open source dynamic translator, QEMU, as the first step. And it describes the software development and testing/debugging on the developed emulator.