• Proceedings of the Korean Information Science Society Conference
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• 2006.10d
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• pp.30-33
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• 2006

RFID(Radio Frequency Identification)은 RF주파수를 이용해서 사물이나 사람의 정보를 인식하는 자동인식 기술이다. 이 기술은 무선 주파수를 사용해서 대량의 사물을 동시에 인식 할 수 있다는 장점이 있지만, 무선 주파수를 사용하기 때문에, 프라이버시 문제와 주파수 충돌문제와 같은 부수적인 단점을 가지고 있다. 리더 충돌문제를 해결하기 위한 여러 가지 많은 연구들이 진행 되고 있지만, 현재까지 연구된 대부분은 고정적인 환경에서의 해결 방법들이다. 본 논문에서는 앞으로 다가올 모바일 사회에 대비해서, 밀집된 모바일 환경에서의 리더 충돌 방지 기법을 제안한다. 이 기법은 모바일 리더의 위치를 계산하고, 적절한 주파수를 할당하고 동적으로 RF의 세기를 조절함으로써 리더의 충돌을 방지 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.311-312
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• 2011

스마트폰의 응용프로그램 별 전력 소비 정보는 전력 관리를 하는데 있어 유용한 정보가 된다. 응용프로그램 별 소비 전력을 측정하는 현실적인 방법은 응용프로그램 별 전력 소비 모델을 세운 뒤 추정하는 것이다. 특히 프로세서의 이용률을 통한 소비 전력 모델을 세우면, 운영체제가 제공하는 프로세스 별 CPU 점유 시간을 통해 소비 전력을 쉽게 계산할 수 있다. 본 논문에서는 실험적 방법을 통해 동적 주파수 조절 기법 하에서 CPU 이용률에 따른 프로세서의 전력 소비 모델을 제시한다. 이를 통해 동적 주파수 조절 기법이 적용된 스마트폰에서 응용프로그램 별 전력 소비량을 추정할 수 있다.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.9
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• pp.1405-1411
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• 2022

Power management is still an important issue in embedded environments as hardware advances like high-performance processors. Power management methods such as DVFS control CPU frequencies in an adaptive manner for efficient power management in polling-based I/O programs such as network communication. This paper presents the problems of the existing power management method and proposes a new power management method. Through this, it is possible to reduce electric consumption by increasing the polling cycle in situations where the frequency of data reception is low, and on the contrary, in situations where data reception is frequent, it can operate at the maximum frequency without performance degradation. After implementing this as a code layer on the embedded board and observing it through Atmel's Power Debugger, the proposed method showed a performance improvement of up to 30% in energy consumption compared to the existing power management method.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.104-111
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• 2010

This paper presents an adaptive image enhancement method using the spatial frequency property in the DCT(discrete cosine transform) compressed domain. The dc coefficients, the illumination components of image, are adjusted to compress the dynamic range of image, and the ac coefficients are modified to enhance the contrast by using the human visual system(HVS) and the spatial frequency property. The ac coefficients are separated into vertical direction, horizontal direction, and mixed spatial frequency components, and adaptively modified to minimize the block artifacts that possibly occur in the image enhancement. The proposed method using dynamic range compression and adaptive contrast enhancement shows the advanced performance without the block artifact compared with existing method.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.641-650
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• 2008

As portable devices are used widely, power management algorithm is essential to extend battery use time on small-sized battery power. Although many methods have been proposed, they assumed the voltage transition overhead was negligible or was considered partially. However, the voltage transition overhead might not guarantee to schedule real-time tasks in portable multimedia systems. This paper proposes the adaptive power-aware algorithm to minimize the power consumption by considering the voltage transition overhead. It selects only a few discrete frequencies from the whole frequencies of a system and adjusts the interval between two consecutive frequencies based on the system utilization to reduce the number of frequency change. This algorithm saves the power consumption about 10 to 25 percent compared to a CC RT-DVS method and a frequency-smoothing method.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.517-526
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• 2008

As the functionality of portable devices arc being enhanced and the performance is being greatly improved, power dissipations of battery driven portable devices are being increased. So, an efficient power management for reducing their power consumption is needed. In this paper, we propose a window-based DVS algorithm for MPEG Player. The proposed algorithm maintains the recently frame information and execution time received from MPEG player in window queue and dynamically adjusts (frequency, voltage) level based on window queue information. Our algorithm can be implemented in the common multimedia player as a module. We employed well-known MPlayer for the measurement of performance. The experimental result shows that the proposed algorithm reduces energy consumption by 56% on maximal performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2401-2409
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• 2016

Android CPU governors exploit the DVFS (Dynamic Voltage Frequency Scaling) technique. The DVFS is a power management technique where the CPU operating frequency is decreased to allow a corresponding reduction in the CPU supply voltage. The power consumed by a CPU is approximately proportional to the square of the CPU supply voltage. Therefore, lower CPU operating frequency allows the CPU supply voltage to be lowered. This helps to reduce the CPU power consumption. However, lower CPU operating frequency increases a task's execution time. Such an increase in the task's execution time makes the task's response time longer and makes the task's deadline miss occur. This finally leads to degrading the quality of service provided by the task. In this paper, we evaluated the performance of Android CPU governors in terms of the power consumption, tasks's response time and deadline miss ratio.

• Journal of Korean Society of Steel Construction
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• v.20 no.4
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• pp.455-467
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• 2008

The dynamic vehicle running tests were performed to analyze dynamic behavioral characteristics such as displacement, strain history loop and vibration acceleration in arch bridges. Also, the validity of the modeling was verified by comparing the results of the tests and those of the structural analysis modeling. With the resonance revision of verified modeling, when the ratio of excited frequencies to natural frequencies exceeds ${1{\pm}0.04}$, the stability of the bridge is obtained. Also, in the event of resonance by speed parameter, the second mode shape is dominant to the dynamic behaviors of arch bridges. It is found that manipulating the parameters involving arch ribs can increase the second mode natural frequency. It makes critical velocity greater than operational velocities to guarantee the stability of arch bridges.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.