• Title/Summary/Keyword: 동작 분할

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Sliding-DFT based multi-channel phase measurement FPGA system (Sliding-DFT를 이용한 다채널 위상 측정 FPGA 시스템)

  • Eo, Jin-Woo;Chang, Tae-Gyu
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.128-135
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    • 2004
  • This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

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Design and Implementation of a Systolic Architecture for Low Power Wireless Sensor Network (저 전력 무선 센서 네트워크를 위한 시스톨릭 구조 설계 및 구현)

  • Lee, Kyung-Hoon;Lee, Hak-Jai;Kim, Young-Min
    • The Journal of the Korea institute of electronic communication sciences
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    • v.10 no.6
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    • pp.749-756
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    • 2015
  • In this paper, we propose a unique systolic structure and communication algorithm that maintains a solid link between nodes using synchronous digital communication and enables low power communication. This system was designed by using CC2500 RF transceiver, CC2590 RF front end and C8051F330 low power microcontroller. The measurement of power consumption in the network link shows below $400{\mu}W$ in data transfer rate 320bps. The system constitutes the base unit of low power wireless network that was composed of each seven link nodes having eight sensor nodes. Results of the experiments show that link nodes using a 4Ah battery could operate over 3 years without replacement.

Development of Hybrid Power Storage System for Urban Railway with UPS Function for Emergency Power Generation (비상발전용 UPS 기능을 갖춘 도시철도용 복합형 전력저장시스템 개발)

  • Hong, Kyungjin
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.6
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    • pp.191-196
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    • 2019
  • In the case of urban railway facilities, the power supply should be maintained for the safe movement of passengers in communication facilities, disaster prevention facilities and boarding area security because of the confusion when power supply is cut off due to the nature of public transportation. In addition, considering that the number of trains is running on the urban railway line, it is necessary to operate at least 30 minutes for the bus stop and at least 1 hour for the communication and disaster prevention facilities. Therefore, it is essential to supply emergency power source to maintain stable operation of induction lamp and smoke exhaust system because main power is cut off in order to prevent further spread due to fire in case of the history of urban railway section or vehicle fires. Recently, UPS(Uninterruptible Power Supply) function to prevent power outage in emergency, emergency power generation combined with ESS function which saves electricity at nighttime price time, A hybrid power storage system with a UPS function.

Low Energy Motion Estimation Architecture using Energy Management Algorithm (에너지 관리 알고리즘을 이용한 저전력 움직임 추정기 구조)

  • Kim Eung-sup;Lee Chanho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.8C
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    • pp.793-800
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    • 2005
  • Computation of multimedia data increases in portable devices with the advances of the mobile and personal communication services. The energy management of such devices is very important for the battery-powered operation hours. The motion estimation in a video encoder requires huge amount of computation, and hence, consumes the largest portion of the energy consumption. In this paper, we propose a novel architecture that a low energy management scheme can be applied with several fast-search algorithms. The energy-constrained Vdd hopping (ECVH) technique reduces power consumption of the motion estimation by adaptively changing the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget. We show that the ECVH can be applied to the architecture, and that the power consumption can be efficiently reduced.

Face and Hand Tracking Algorithm for Sign Language Recognition (수화 인식을 위한 얼굴과 손 추적 알고리즘)

  • Park, Ho-Sik;Bae, Cheol-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.11C
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    • pp.1071-1076
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    • 2006
  • In this paper, we develop face and hand tracking for sign language recognition system. The system is divided into two stages; the initial and tracking stages. In initial stage, we use the skin feature to localize face and hands of signer. The ellipse model on CbCr space is constructed and used to detect skin color. After the skin regions have been segmented, face and hand blobs are defined by using size and facial feature with the assumption that the movement of face is less than that of hands in this signing scenario. In tracking stage, the motion estimation is applied only hand blobs, in which first and second derivative are used to compute the position of prediction of hands. We observed that there are errors in the value of tracking position between two consecutive frames in which velocity has changed abruptly. To improve the tracking performance, our proposed algorithm compensates the error of tracking position by using adaptive search area to re-compute the hand blobs. The experimental results indicate that our proposed method is able to decrease the prediction error up to 96.87% with negligible increase in computational complexity of up to 4%.

Design of Miniaturized Magnetic Field Probe for Measurement of IC Surface Current Distribution (IC 표면 전류 분포 측정을 위한 초소형 자기장 프로브 설계)

  • Lee, Seung-Bae;Jeon, Young-Hyun;Kim, Byung-Sung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.5
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    • pp.154-161
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    • 2009
  • Recently, as many functional blocks are integrated on a small area the high speed integrated circuits emerge as a critical electromagnetic interferer which causes mal-function of adjacent circuitries and lowers the sensitivity of the wireless receivers. Therefore, it is necessary to devise an precise analyzing tool to pinpoint the major electromagnetic noise contributor among the internal circuit blocks of high speed IC's. This paper presents the design, fabrication, and measurement results of the high resolution magnetic field probe which can measure the current density on the IC surface. In order to achieve the high resolution, the magnetic field probe is fabricated using 3-metal semiconductor process so that its thickness is reduced by 10% than that of conventional works. Through the magnetostatic analysis and EM simulation, spatial resolution and sensitivity to the nonmagnetic field components are analyzed. Experimentally, it is found that the fabricated probe can measure the current density on the IC surface with $210{\mu}m$-spatial-resolution.

Design of Asynchronous 16-Bit Divider Using NST Algorithm (NST알고리즘을 이용한 비동기식 16비트 제산기 설계)

  • 이우석;박석재;최호용
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.3
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    • pp.33-42
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    • 2003
  • This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

A Robust Object Extraction Method for Immersive Video Conferencing (몰입형 화상 회의를 위한 강건한 객체 추출 방법)

  • Ahn, Il-Koo;Oh, Dae-Young;Kim, Jae-Kwang;Kim, Chang-Ick
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.48 no.2
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    • pp.11-23
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    • 2011
  • In this paper, an accurate and fully automatic video object segmentation method is proposed for video conferencing systems in which the real-time performance is required. The proposed method consists of two steps: 1) accurate object extraction on the initial frame, 2) real-time object extraction from the next frame using the result of the first step. Object extraction on the initial frame starts with generating a cumulative edge map obtained from frame differences in the beginning. This is because we can estimate the initial shape of the foreground object from the cumulative motion. This estimated shape is used to assign the seeds for both object and background, which are needed for Graph-Cut segmentation. Once the foreground object is extracted by Graph-Cut segmentation, real-time object extraction is conducted using the extracted object and the double edge map obtained from the difference between two successive frames. Experimental results show that the proposed method is suitable for real-time processing even in VGA resolution videos contrary to previous methods, being a useful tool for immersive video conferencing systems.

A Study on protocol analysis between KTX control system and sub-devices (고속열차(KTX)제어시스템과 하부장치간 프로토콜 분석연구)

  • Kim, Hyeong-In;Jung, Sung-Youn;Kim, Hyun-Shik;Jung, Do-Won;Kim, Chi-Tae;Kim, Dong-Hyun
    • Proceedings of the KSR Conference
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    • 2007.11a
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    • pp.179-186
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    • 2007
  • KTX control systems mutually control OBCS, ATC, MBU, TECA, MDT, ABU, HVAC, TRAE, PID and FDTR, KTX OBCS as master, and controls other sub-control devices as slave, using various serial lines. In order to analyze physical structure of various serial link lines and mutual data transmission structure, serial line analyzer is used in many ways. To use serial line analyzer, prior and professional technics about High Speed Train and experience of using device are necessary. In spite of difficult situation of space and environment where we work for maintenance of High Speed Train, in presenting basic structure about physical connection method aquired by sub-device serial line data collection and about communication data analysis, I hope that this research will be helpful for the person who work for similar area. Also, I hope that this research will help diagnostic work of High Speed Train, which is necessary for test run of independently developed High Speed Train.

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The Effects of Dual Task Training on the Balance, Upper Extremity Function, and Activities of Daily Living in the Chronic Stroke Patients (이중과제 훈련이 만성 뇌졸중 환자의 균형, 상지기능, 일상생활활동 수행능력에 미치는 효과)

  • Yu, Ji-Ae;Park, Ju-Hyung
    • Journal of Convergence for Information Technology
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    • v.10 no.6
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    • pp.217-227
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    • 2020
  • This study investigated the effects of dual task training on balance, upper extremity motor function and activities of daily living in patients with chronic stroke. The study subjects were 14 chronic stroke patients. dual task training groups(n=7), and single task training groups(n=7). The intervention period was conducted for 3 times a week, 30 minutes per session, and 4 weeks for all groups. To measure the BT4, JTT, K-MBI were used before and after the intervention. Dual task training groups showed a significant increase in BT 4 and JTT scores(p<.05). The difference between the two groups was significant in the BT4 and JJT scores(p<.05). There was a score improvement in K-MBI, but there was no statistically significant difference(p>.05) Dual task training was effective in facilitating balance, upper extremity function and activities of daily living in patients with chronic stroke.