• The Journal of the Acoustical Society of Korea
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• v.25 no.2
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• pp.96-100
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• 2006

Kim et al. Proposed Normalized Confidence Measure (NCM) [1-2] and it was successfully used for rejecting mis-recognized words in isolated word recognition. However their experiments were performed on the fixed word speech recognition. In this Paper we apply NCM to the domain of vocabulary independent speech recognition (VISP) and shows the rejection Performance of NCM in VISP. Specialty we Propose vector quantization (VQ) based method for overcoming the problem of unseen triphones. It is because NCM uses the statistics of triphone confidence in the case of triphone-based normalization. According to speech recognition experiments Phone-based normalization method shows better results than RLJC[3] and also triphone-based normalization approach. This results are different with those of Kim et al [1-2]. Concludingly the Phone-based normalization shows robust Performance in VISP domain.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.135-149
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• 2000

Most of prior works on testing parallel programs have concentrated on how to guarantee the reproducibility by employing event traces exercised during executions of a program. Consequently, little work has been done to generate test cases, especially, from specifications produced from software development process. In this research work, we devise the techniques for deriving test cases automatically from the specifications written in Message Sequence Charts(MSCs) which are widely used in telecommunication areas and develop the testing environment for performing module testing of parallel programs with derived test cases. For deriving test cases from MSCs, we have to uncover the causality relations among events embedded implicitly in MSCs. For this, we devise the methods for adapting vector time stamping to MSCs, Then, valid event sequences, satisfying the causality relations, are generated and these are used as test cases. The generated test cases, written in TTCN, are translated into CHILL source codes, which interact with a target module to be tested and test the validity of behaviors of the module. Since the testing method developed in this research work extracts test cases from the MSC specifications produced front telecommunications software development process, it is not necessary to describe auxiliary specifications for testing. In audition adapting vector time stamping generates automatically the event sequences, the generated event sequences that are ones for whole system can be used for individual testing purpose.

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.51-56
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• 2003

The structuring of Web information supports a strong user side viewpoint that a user wants his/her own needs on snooping a specific Web site. Not only the depth first algorithm or the breadth-first algorithm, but also the Web information is abstracted to a hierarchical structure. A prototype system is suggested in order to visualize and to represent a semantic significance. As a motivating example, the Web test site is suggested and analyzed with respect to several keywords. As a future research, the Web site model should be extended to the whole WWW and an accurate assessment function needs to be devised by which several suggested models should be evaluated.

• Journal of the Korea Computer Graphics Society
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• v.26 no.3
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• pp.123-131
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• 2020

This study proposes a real-time rendering algorithm for lighting when each of more than 100,000 moving particles exists as a light source. Two 3D textures are used to dynamically determine the range of influence of each light, and the first 3D texture has light color and the second 3D texture has light direction information. Each frame goes through two steps. The first step is to update the particle information required for 3D texture initialization and rendering based on the Compute shader. Convert the particle position to the sampling coordinates of the 3D texture, and based on this coordinate, update the colour sum of the particle lights affecting the corresponding voxels for the first 3D texture and the sum of the directional vectors from the corresponding voxels to the particle lights for the second 3D texture. The second stage operates on a general rendering pipeline. Based on the polygon world position to be rendered first, the exact sampling coordinates of the 3D texture updated in the first step are calculated. Since the sample coordinates correspond 1:1 to the size of the 3D texture and the size of the game world, use the world coordinates of the pixel as the sampling coordinates. Lighting process is carried out based on the color of the sampled pixel and the direction vector of the light. The 3D texture corresponds 1:1 to the actual game world and assumes a minimum unit of 1m, but in areas smaller than 1m, problems such as stairs caused by resolution restrictions occur. Interpolation and super sampling are performed during texture sampling to improve these problems. Measurements of the time taken to render a frame showed that 146 ms was spent on the forward lighting pipeline, 46 ms on the defered lighting pipeline when the number of particles was 262144, and 214 ms on the forward lighting pipeline and 104 ms on the deferred lighting pipeline when the number of particle lights was 1,024766.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.424-426
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• 1998

공간정보의 효율적 공유를 위해 인터넷 기반 GIS소프트웨어 개발 및 응용과 관련된 연구가 활발히 진행 중에 있다. 여러 인터넷 GIS의 기본적인 요구사항 및 현재까지 개발모델과 문제점을 살펴보고, 표준 인터넷 기술을 기반으로 최근 웹 기술 표준 동향을 포함한, OpenGIS상호 운용성이 지원되는 인터넷 GIS기본 구조를 제시하고자 한다. 표준화될 인터넷 GIS 속도 향상과 TCP/IP상의 보안문제가 해결되어야 하고, OpenGIS에서 구성하고 있는 공간 데이터 공유를 위한 표준 사양을 준수할 뿐 아니라 클라이언트/서버의 부하가 최적화된 구조여야한다. 특히 웹 중심의 각종 인터넷 기술들, 즉 HTTP NG. XML, SSL등의 표준 기술이 함께 적용되어야 한다. 새로운 인프라구조는 GIS D/B에 포함된 확장된 (Enhanced) HTTP/MAP 서버와 클라이언트로 구성된다. MAP클라이언트는 MIME-TYPE 에 따라 GIS데이터를 표시할 수 있는 윈도우 환경으로 변환되며 GIS 데이터셋은 XML을 기반으로 하는 MapML(Mapping Makup Language)를 통해 형식을 정한다. 클라이언트가 MapML 토큐먼트를 통해 정의된 구획의 레이어와 벡터 데이터를 요청하고, Map서버는GIS D/B에서 WKB 혹은 소위 VML 형태로 추출하여 클라이언트로 보내주게 된다. 주어진 구획은 MapML로 정의된 속성들을 통해 각종 부가 정보를 열람할 수 있다. MAP은 HTTP와 같은 형태로 동작하므로 전자인증, 암호화를 통한 GIS정보 보안, 클라이언트와 서버 부하의 효율적인 분배 XML을 통한 다양한 GIS속성표현이 가능하다. 본 구조는 Apache +Amiya + Crass D/B+ MapML 환경에서 구현되고 있다.팔일 전송 기법을 각각 제시하고 실험을 통해 이들의 특성을 비교분석하였다.미에서 uronic acid 함량이 두 배 이상으로 나타났다. 흑미의 uronic acid 함량이 가장 많이 용출된 분획은 sodium hydroxide 부분으로서 hemicellulose구조가 polyuronic acid의 형태인 것으로 사료된다. 추출획분의 구성단당은 여러 곡물연구의 보고와 유사하게 glucose, arabinose, xylose 함량이 대체로 높게 나타났다. 점미가 수가용성분에서 goucose대비 용출함량이 고르게 나타나는 경향을 보였고 흑미는 알칼리가용분에서 glucose가 상당량(0.68%) 포함되고 있음을 보여주었고 arabinose(0.68%), xylose(0.05%)도 다른 종류에 비해서 다량 함유한 것으로 나타났다. 흑미는 총식이섬유 함량이 높고 pectic substances, hemicellulose, uronic acid 함량이 높아서 콜레스테롤 저하 등의 효과가 기대되며 고섬유식품으로서 조리 특성 연구가 필요한 것으로 사료된다.리하였다. 얻어진 소견(所見)은 다음과 같았다. 1. 모년령(母年齡), 임신회수(姙娠回數), 임신기간(姙娠其間), 출산시체중등(出産時體重等)의 제요인(諸要因)은 주산기사망(周産基死亡)에 대(對)하여 통계적(統計的)으로 유의(有意)한 영향을 미치고 있어 $25{\sim}29$세(歲)의 연령군에서, 2번째 임신과 2번째의 출산에서 그리고 만삭의 임신 기간에, 출산시체중(出産時體重) $3.50{\sim}3.99kg$사이의 아이에서 그 주산기사망률(周産基死亡率)이 각각 가장 낮았다. 2. 사산(死産)과 초생아사망(初生兒死亡)을 구분(區分)하여 고려해 볼때 사산(死産)은 모성(母

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.11
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• pp.861-869
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• 2020

A dynamo set for a high-power induction motor drive is expensive and needs a long time to manufacture. Therefore, the development of a simulator that functions as the induction motor and load equipment is required. A load simulator of an inverter for a high-power three-phase induction motor consists of a reactor and three-phase PWM inverter. Therefore, it cannot simulate the dynamic characteristics of an induction motor and functions only as a load. In this paper, a real-time simulator is proposed to simulate a model of an induction motor and the load characteristics based on an LCL filter and three-phase PWM rectifier for a three-phase induction motor. The currents of a PWM inverter that simulate the stator currents of the motor are controlled by the inductor currents and capacitor voltages of the LCL filter. The capacitor voltages of the LCL filter simulate the induced voltages in the stator windings by the rotating rotor fluxes of the motor, and the capacitor voltages are controlled by the inductor currents and a PWM rectifier. The rotor currents, the stator and rotor flux linkages, the electromagnetic torque, the slip frequency, and the rotor speed are derived from the inverter currents and the motor parameters. The electrical and mechanical model characteristics and the operation of vector control were verified by MATLAB/Simulink simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.29-45
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• 2017

Ad hoc sensor network is characterized by decentralized structure and ad hoc deployment. Sensor networks have all basic features of ad hoc network except different degrees such as lower mobility and more stringent energy requirements. Existing protocols provide different tradeoffs among some desirable characteristics such as fault tolerance, distributed computation, robustness, scalability and reliability. wireless protocols suggested so far are very limited, generally focusing on communication to a single base station or on aggregating sensor data. The main reason having such restrictions is due to maximum lifetime to maintain network activities. The network lifetime is an important design metric in ad hoc networks. Since every node does a router role, it is not possible for other nodes to communicate with each other if some nodes do not work due to energy lack. In this paper, we suggest an experimental ad-hoc on-demand distance vector routing protocol to optimize the communication of energy of the network nodes.The load distribution avoids the choice of exhausted nodes at the route selection phase, thus balances the use of energy among nodes and maximizing the network lifetime. In transmission control phase, there is a balance between the choice of a high transmission power that lead to increase in the range of signal transmission thus reducing the number of hops and lower power levels that reduces the interference on the expense of network connectivity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.82-90
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• 2011

Because of the development of Smart phone devices, the demands of high performance FPU(Floating-point Unit) becomes increasing. Therefore, we propose the high-speed single-/double-precision FPU design that includes an elementary add/sub unit and improved multiplier and compare and convert units. The most commonly used add/sub unit is optimized by the parallel rounding unit. The matrix operation is used in complex calculation something like a graphic calculation. We designed the Multiply-Add Fused(MAF) instead of multiplier to calculate the matrix more quickly. The branch instruction that is decided by the compare operation is very frequently used in various programs. We bypassed the result of the compare operation before all the pipeline processes ended to decrease the total execution time. And we included additional convert operations that are added in IEEE754-2008 standard. To verify our RTL designs, we chose four hundred thousand test vectors by weighted random method and simulated each unit. The FPU that was synthesized by Samsung's 45-nm low-power process satisfied the 600-MHz operation frequency. And we confirm a reduction in area by comparing the improved FPU with the existing FPU.