• Journal of Broadcast Engineering
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• v.19 no.2
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• pp.158-165
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• 2014

High Efficiency Video Coding (HEVC), the latest video coding standard, has twice of the compression efficiency compared to AVC/H.264 under the same image quality condition. To obtain the improved efficiency, however, it was adopted for many methods which need complicated calculation, and the time complexity of HEVC was increased more than that of AVC/H.264. To solve this problem, the various fast algorithms have been researched. In this paper, we propose a fast intra prediction mode decision method which uses result of Rough Mode Decision (RMD) and Most Probable Mode (MPM). The proposed method selects a best predicted mode by comparing each predicted directions which are calculated through RMD and MPM. We applied the proposed method to HM 10.0 and conducted an comparing experiment in All-Intra environment. The experiment result showed that total encoding time is reduced by about 26% on average with about a 0.8% loss of BD-rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.41-52
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• 2009

In Motion JPEG2000 encoding, huge bandwidth requirement of data memory access is the bottleneck in required system performance. For the alleviation of this bandwidth requirement, a new embedded compression(EC) algorithm with a little bit of image quality drop is devised. For both random accessibility and low latency, very simple and efficient entropy coding algorithm is proposed. We achieved significant memory bandwidth reductions (about 53${\sim}$81%) and reduced code-block memory to about half size through proposed multi-mode algorithms, without requiring any modification in JPEG2000 standard algorithm.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.271-282
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• 2013

Recently, ITU-T/VCEG and ISO/IEC MPEG have started a new joint standardization activity on video coding, called High Efficiency Video Coding (HEVC). This new standard gives significant improvement in terms of picture quality for high resolution video. The main challenge in this upcoming standard is the time complexity. In this paper we have focused on CU splitting algorithm. We have proposed a novel algorithm which can terminate the CU splitting process early based on the RD cost of the parent and current level and the motion vector value of the current CU. Experimental result shows that our proposed algorithm gives on average more than about 10% decrement in time over ECU [8] with on average 1.78% of BD loss on the original.

• Journal of Broadcast Engineering
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• v.20 no.3
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• pp.449-463
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• 2015

Video object tracking is important for variety of applications, such as security, video indexing and retrieval, video surveillance, communication, and compression. This paper proposes an object tracking method in HEVC bitstreams. Without pixel reconstruction, motion vector (MV) and size of prediction unit in the bitstream are employed in an Spatio-Temporal Markov Random Fields (ST-MRF) model which represents the spatial and temporal aspects of the object's motion. Coefficient-based object shape adjustment is proposed to solve the over-segmentation and the error propagation problems caused in other methods. In the experimental results, the proposed method provides on average precision of 86.4%, recall of 79.8% and F-measure of 81.1%. The proposed method achieves an F-measure improvement of up to 9% for over-segmented results in the other method even though it provides only average F-measure improvement of 0.2% with respect to the other method. The total processing time is 5.4ms per frame, allowing the algorithm to be applied in real-time applications.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.450-456
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• 2010

In the high-speed packet service, next generation mobile communication system has emerged as a major feature. If the fire of these high-speed kit services and non-continuous transmission of data due to the symmetrical nature of daeyiteo traffic for D-CDMA system has been actively studied. Small amounts of data moving in the uplink, but the real-time video downlink transmission, such as downloading large files to move data and services to those with asymmetric traffic characteristics, a system that can efficiently handle the data requirements be. Of 3GPP TDD(Time Division Duplex) scheme based on CDMA and TDMA in a way by introducing the concept through the proper allocation of time slots that can handle asymmetric traffic efficiently, has an advantage. TD-CDMA system by considering the characteristics of the frame configuration of transmission methods, such as physical channel structure and channel coding has been investigated. In addition, the HARQ scheme TD-CDMA system performance is analyzed by comparing them.

• The KIPS Transactions:PartB
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• v.9B no.5
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• pp.571-578
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• 2002

In this paper, we propose a video sequence coding scheme called AMV (Auxiliary Motion Vector) to minimize error propagation caused by transmission errors over the Internet. Unlike the conventional coding schemes the AMY coder, for a macroblock in a frame, selects two best matching blocks among several preceding frames. The best matching block, called a primary block, is used for motion compensation of the destination macroblock. The other block, called an auxiliary block, replaces the primary block in case of its loss at the decoder. When a primary block is corrupted or lost during transmission, the decoder can efficiently and simply suppress error propagation to the subsequent frames by replacing the block with an auxiliary block. This scheme has an advantage of reducing both the number and the impact of error propagations. We implemented the proposed coder by modifying H.263 standard coding and evaluated the performance of our proposed scheme in the simulation. The simulation results show that AMV coder is more efficient than the H.263 baseline coder at the high packet loss rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.145-155
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.