• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.4
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• pp.312-321
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• 2013

In this paper, high efficiency control method for flyback inverter with synchronous rectifier(SR) based on photovoltaic AC modules is proposed. In this control method, the operation of SR is classified according to the voltage spike across main switch SP. When the voltage spike across SP is lower than the rating voltage of SP, the operation of active clamp circuit is interrupted for reducing the switching loss of auxiliary switch. In this time, the SR is operated for soft-switching of SP. When the voltage spike across Sp is higher than the rating voltage of SP, the operation of active circuit is activated for reducing the voltage spike. The SR is operated for reducing the conduction loss of secondary output diode. Thus, a switching loss of the main switch can be reduced in low power region, and weighted-efficiency can be improved. A theoretical analysis and the design principle of the proposed method are provided. And validity is confirmed through simulation and experimental results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.10
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• pp.26-36
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• 2000

In this paper, we design the nonoverlapping multicarrier modulation (MCM) system for high rate paging system and evaluate the Performance by computer simulation. In conventional paging system, FSK was usually used, but we select QAM for high bandwidth efficiency. Transmitter structure adopts that of 4-16QAM of the iDEN$\^$TM/ and receiver consists of symbol timing recovery, carrier recovery and automatic gain control. In addition, pilot symbol aided modulation (PSAM) which can overcome the simulcast fading channel is considered and we also propose the optimum pilot symbol pattern. Finally, we show the performance of the overall 4-16QAM system by computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.597-604
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• 2019

In this paper, we propose an improved method on an adaptive application of the CPP(Chinese Postman Problem) algorithm to the protocol test suite generation for conformance testing. Also, we present an example application of this CPP algorithm to B-ISDN Q.2931 call/connection control procedure for the purpose of showing how it can be adapted to generate a test suite for conformance testing of a communication protocol. The proposed method has an advantage of an optimization technique which finds a minimum cost of test suite from a standardized specification, so this optimization technique of the CPP algorithm can be practically applied to a real environment for testing a conformity of a protocol implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.9
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• pp.1304-1314
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• 1993

During the last several years, the demand of mobile communication is increasing rapidly due to the convenience of usage. Therefore, the evoluation scenario toward the new cellular network is needed. In this paper, the future prospect of cellular network is considered, and movable-boundary TDMA/BTMA protocol is proposed as a new voice/data integrated multiple access protocol for the future cellular packet radio networks. Then, the performance of movable-bounary TDMA/BTMA protocol is analyzed and compared with that of PRMA protocol by computer simulation. In the proposed movable-boundary TDMA/BTMA protocol, the voice traffic sensitive to delay time is served by TDMA protocol and the data traffic sensitive to loss is served by BTMA protocol. Also, the boundary of voice and data can be moved adaptively by usign SYN character, control byte, voice call counter, ect. Therefore. it could be seen that the performance of movable-boundary TDMA/BTMA protocol is better than that of PRMA protocol with respect to delay and throughput.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.9-17
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• 2007

This paper introduces a Petri Net-based multimedia programming method. For this purpose, we are proposing MPN(Multimedia Petri Net) which can be used for representing a multimedia scenario. We are also introducing methods to analyze a MPN with which we can detect some kinds of design faults in the scenario. A multimedia program replays the scenario by interpreting the MPN. A method to implement such a multimedia program is also discussed. Our multimedia program provides the manipulation functions of stop, play, fast forward. rewind, and fast rewind. There are many varieties of Petri Net. Several of them are for modeling multimedia scenarios. They all have been used for synchronization analysis. But none of them were used for replaying multimedia scenario. We have extended these nets to MPN. A MPN model contains not only the flow of a scenario but also all the information associated with the data units. Therefore, our player can play the multimedia scenario by interpreting the MPN.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.219-225
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• 2014

The purpose of this paper is to control of the low-speed, high-precision PMSM 2-axes pitch/turning. In this paper, apply the PAM-PWM inverter for it. However, The PAM-PWM inverter, control algorithms and hardware is complex. But it is possible to improve the performance in the low-speed operation can reduce the effect of the PWM ripple and Dead Time of inverter by applying suitable DC-bus voltage control. The direct driver PMSM(Permanent Magnet Synchronous Motor) configured to vector control part, PAM control part and the other controller. The vector control part includes PI current, speed control, additional space vector modulation. PAM control part has to have PI voltage controller and P current controller for DC-bus voltage control. Besides, the motor position estimator, the speed estimator and the counter electromotive force and Dead Time Compensation are added. With this arrangement, PMSM was driven with a low pole pitch/turning by performing the current control to the current command or torque command is the paper. As a result, it was possible to minimize the disturbance component that appears in the drive in proportion to the DC voltage magnitude. The use of a hydraulic drive method for a two-axis bubble column is a typical tank. When using the PWM PAM inverter driver is in the turret can be driven by high-precision, low vibration, low noise compared to the hydraulic drive may contribute to the computerization of the turret.

• Journal of Korean Tunnelling and Underground Space Association
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• v.25 no.3
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• pp.245-259
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• 2023

The purpose of this paper is to examine the most recent tunnel scanning systems to obtain insights for the development of non-contact mobile inspection system. Tunnel scanning systems are mostly being developed by adapting two main technologies, namely laser scanning and image scanning systems. Laser scanning system has the advantage of accurately recreating the geometric characteristics of tunnel linings from point cloud. On the other hand, image scanning system employs computer vision to effortlessly identify damage, such as fine cracks and leaks on the tunnel lining surface. The analysis suggests that image scanning system is more suitable for detecting damage on tunnel linings. A camera-based tunnel scanning system under development should include components such as lighting, data storage, power supply, and image-capturing controller synchronized with vehicle speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.