• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.15-21
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• 2007

In this paper, we propose a technique of a practical symbol acquisition and tracking using a low complex ADC and simple digital circuits for noncoherent asynchronous impulse-radio-based Ultra Wideband (IR-UWB) receiver based on energy detection. Compared to previous approaches of detecting an exact acquisition time that require much hardware resource, the proposed technique is to detect the target symbol by finding the symbol acquisition interval per symbol with a target symbo, thus the complexity of the complete signal processing and power consumption by ADC are reduced. To do this, we define the bit decision window (BDW) and analyze the relation between SNR, hardware resource, size of BDW and BER(Bit Error Rate). Using the results, the optimum BDW size for the minimum BER with limited hardware resource is selected. The proposed synchronization technique is verified with an aid of a simulator programmed by considering practical impulse channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.57-64
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• 2004

In this paper, we propose a RZ/HRZ mixture data transmission method for the asynchronous circuit design to reduce Power consumption. The dual-rail data with Rf decoding scheme is used to design asynchronous circuit, and it is easy to get a completion signal of the data validity from the native data as contrasted with sin91e-rail. However, the dual-rail scheme suffers from large chip area and increasing of Power consumption from all signals by the switching of the return-to-zero. We need to diminish number of circuit switching. The proposed RZ/HRZ data transmission reduces a switching activity to about 50% and it shows 23% lower power consumption than the conventional dual-rail coding with RZ's.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.4
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• pp.17-23
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• 2012

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.164-165
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• 2019

본 논문은 3상 동기발전기의 과도 특성을 분석하기 위해 MATLAB/ SIMULINK를 이용하여 모델링하였으며 동기발전기 출력단의 개방 및 3상 단락 회로 조건에 따른 특성곡선을 분석하였다. 정상상태, 과도상태 및 차과도상태 구간에서 고정자 권선, 회전자 권선 및 댐퍼 권선 등이 갖는 자기 인덕턴스 및 상호 인덕턴스 특성 관계와 자속 변화특성 등을 수학적 모델 기반의 소신호 모델링을 통해 3상 동기발전기를 등가적으로 모델링하였다. 시뮬레이션을 통해 얻은 값에 의해 과도상태와 차과도상태의 모터 데이터를 분석하고 단락상태의 시간 상수를 계산하여, 동기발전기의 3상 단락 조건에서 초기 과도 및 과도상태의 특성을 검증하였다.최종적으로, 이론적 공식에 의해 계산 된 동기 발전기의 파라미터는 시뮬레이션 결과와 일치하며 오차는 2 % 범위 내에 있다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.7
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• pp.9-15
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• 1999

In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digital loop filter is combined with an error symbol detecting circuit. Suppressing the tracking process, when hop mute and impulse noises are detected, improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. Simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.245-251
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• 1997

In designing defibrillator, several parameters such as patient's transthoracic impedance, output energy level, peak current, and time duration of current waveform must be considered to generate optimum electrical shocks on the heart. Patient's transthoracic impendence depends on the physical and health condition of patient. In this study, before the development of a defibrillator, the range of above parameters value as circuit elements was determined to derive optimal waveform by predicting and analyzing the performance of designed circuit by means of simulation with the software, P-Spice. The efficiency of parameter design was verified through the performance test with the developed defibrillator.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.400-410
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• 1988

In this paper, a fast synchronization system using SAW TDL matched filter and SAW recirculation loop not only for acquisition but also tracking in the direct sequence spread spectrum communication receiver in case of low SNR was designed and its characteristics were investigated. When signal of 16dB SNR was inputed at the receiver, the PN code of the receiver could be synchronized from the extracted signal for synchronization through SAW TDL matched filter and SAM recirculation loop for 30 recirculations. And the average synchronization time of this system was calculated. From the results, we found that this synchronization system could achieve faster synchronization of PN codes in the receiver under the circumstances of low SNR than that of using only matched filter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.6-12
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• 2008

In uplink cable modem link operated in time-division multiple access mode, it is crucial to employ a suitable preamble pattern enabling frame detection, coarse timing/carrier recovery. Preamble pattern based on the constant envelope zero autocorrelation sequence is proposed for the uplink cable modem compliant to the data over cable service interface specification. Frame detection, coarse/fine timing and carrier recovery algorithms suitable for the proposed preamble pattern are also proposed. We check up the performances using numerical results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• NEWSLETTER 전기공업
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• no.97-20 s.189
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• pp.27-39
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• 1997