• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.489-492
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• 1995

This paper has represented the new system for a multibit oversampled sigma-delta A/D convertor. The novel digital correction scheme with the ROM-Table is employed to enhance SNR without requiring accurate precision of the analogue components. This architectures have a good features compared with the 1-bit approach, including significantly lower quantization noise for a given oversampling ratio, as well as improved stability characteristics. Then we have shown the validity of the proposed system by use of the software for the performance evaluation and by realizing the system with SCFs(switched capacitor filter).

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.577-580
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• 2002

본 논문에서는 $\Sigma\Delta$ 변조된 입력신호를 갖는 적응필터의 수렴특성 및 연산량을 향상시키는 방안을 제시하였다. 하드웨어측면에서 효율적인 해상도를 내는 $\Sigma\Delta$ 변조기는 중저파 대역의 신호를 처리하는데 널리 사용되고 있다. $\Sigma\Delta$ 변조신호는 항상 $\pm$1의 값만을 갖기 때문에, 사인알고리즘을 사용하는 적용필터와 효율적으로 결합될 수 있다. 하지만 PCM 신호에 비하여 $\Sigma\Delta$ 변조신호의 상대적인 길이가 길어 이를 처리하는 적응필터의 길이가 증가하고 이에 따른 연산량도 증가하고, 아울러 사인 알고리즘 자체가 갖는 수렴속도의 문제점 때문에 이러한 결합은 불안정한 수렴 특성을 보이게 된다. 본 연구에서는 $\Sigma\Delta$ 변조된 입력신호에 대하여 웨이블릿 변환을 적용한 변환영역 적응필터를 설계하였으며, 필터계수의 일부분만을 주기적으로 갱신함으로써 연산량을 줄이는 방안과 수렴속도의 향상됨을 시스템 식별의 응용 예를 통하여 검증하였다.

• Journal of Welding and Joining
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• v.14 no.3
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• pp.75-85
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• 1996

In this paper the influence of postweld heat treatment on mechanical properties of SMAW and FCAW stainless steel weldments was examined and the obtained results are as follows ; (1) The amount of $\delta$-ferrite formed by SMAW and FCAW process decreased with increasing holding temperature and time in post weld heat treatment(PWHT), and it was found that the reduced ferrite was transformed into sigma phase after $800^{circ}C{\times}50hr$ PWHT. This sigma phase, even though it was very small, resulted in brittleness of dissimilar weldment between carbon steel and stainless steel in bending test, however in similar weldment between stainless steel and stainless steel was not occured. (2) The chemical composition of sigma phase was measured to 28-30%Cr, 7-9%Mo, 4-6Ni in 316L weldment, and also 35-37%Cr, 0.9-1.0Mo, 6-8%Ni in 309L weldment by EDS analysis.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2586-2588
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• 2002

본 논문에서는 $\Sigma\Delta$ 변조된 입력신호를 갖는 적응필터의 수렴특성을 연구하여 향상 방안을 제시하였다. 하드웨어적인 측면에서 효율적인 해상도를 내는 $\Sigma\Delta$ 변조기는 중저주파 대역의 신호를 처리하는데 널리 사용되고 있다. $\Sigma\Delta$ 변조신호는 항상 $\pm1$의 값만을 갖기 때문에, 사인 알고리즘을 사용하는 적응필터와 효율적으로 결합될 수 있다. 하지만, PCM 신호에 대비하여 $\Sigma\Delta$ 변조 신호의 상대적인 길이가 길어 이를 처리하는 적응필터의 길이가 증가하고, 아울러 사인 알고리즘 자체가 갖는 수렴속도의 문제점 때문에 이러한 결합은 불안정한 수렴 특성을 보이게 된다. 본 연구에서는 $\Sigma\Delta$ 변조된 입력신호에 대하여 웨이블릿 변환을 적용한 변환영역 적응필터를 설계하였으며, 수렴속도가 향상됨을 시스템 식별의 응용예를 통하여 검증하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.10
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• pp.513-519
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• 2001

This paper proposed a random sigma-delta modulator(RSDM), which is constructed by a 1st order sigma-delta modulator(SDM) and a simple structured random binary generator(RBG). The 1st order SDM produces a switching pulse waveform which has the same low-frequency component as the reference input, while the RBG spreads the distribution of the number of sampling per switching cycle, and thus disperses the spectrum spikes in the output. The relationship between the harmonic spectra and the number of sampling per switching cycle is studied through computer simulations, and the frequency spectra of the RSDM are confirmed in an experimental setup.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1321-1323
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• 2000

Sigma-delta modulation can perform A/D conversion with a high-resolution. It is useful for simplifing the system and spreading out inband signal noise. When the sigma-delta modulation is applied to a switching converter, it can suppress the harmonic frequencies of output signal and be realized with a simple structure. In this paper, some methods of sigma-delta modulation are discussed so as to find the suitable structure for a switching converter. Noise characteristics are calculated and analyzed through simulations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.1
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• pp.21-27
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• 1997

We have proposed a new structure of the multibit ovesampling sigma-delta modulator. To solve the problkem of requring the accurate precision of the analog components, the novel digital correction scheme with a ROM-table has been employed to enhance the SNR for the proposed system. This architecture has good features compared with the 1-bit approach, including significantly lower quantisation noise for a given oversampling ratio, as well as improve dstability characteristics. Then we hve shown the validity of the proposed system by use of the software developed for the performance evaluation and by realizing the system with SCFs(switched capacitor filters).

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.1250-1252
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• 2003

This Paper presents Sigma-Delta Modulation(SDM) schemes to generate switching waveform for a high-power factor boost-type rectifier. The SDM scheme can be implemented by simple digital algorithm unlike conventional PWM schemes with several hardware, and has the characteristics of spectrum-spreading and noise-shaping effects, which are profitable in harmonic reduction of input current in the boost-type rectifier. The comparison results of their spectrum performances shows that the 1st-order SDM has better harmonic suppression effect than conventional PWM scheme and Dithered SDM scheme.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.455-462
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• 2003

Techniques for the reduction of SRTS jitter and pointer adjustment jitter are studied. To reduce the stuffing jitter several methods have been proposed, such as bit leaking, stuff threshold modulation and sigma delta modulation. The characteristics of jitter generated in SRTS and pointer adjustment systen implementing these reduction techniques is analyzed with computer simulation. The results show that ms jitter value decreases to less than 50% as compared to a conventional pointer adjustment system. The amplitude of SRTS jitter using new techniques decreases or Increases dependent on system parameter.