• Aerospace Engineering and Technology
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• v.4 no.2
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• pp.126-134
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• 2005

Before the launch, launch vehicle is set up a few days ago at launch pad to check process and to supply fuels, etc. During the prelaunch process, the payload is exposed to the thermal environments. The purpose of a prelaunch thermal analysis is to predict maximum/minimum liftoff temperature of payload fairing and to evaluate air conditioning performance. The prelaunch thermal analysis of Delta II PLF is performed using Sinda/fluint, general thermal/fluid analyzer. The results are analyzed and compared with Delta II report.

• Korean Journal of Logic
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• v.16 no.1
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• pp.1-15
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• 2013

Yang [12] investigated weakening-free fuzzy logics expanded by the delta connective $\Delta$, which can be interpreted as Baaz's projection and its generalizations. In this paper, we keep investigating such logics with an alternative delta connective $\Delta$, which can be regarded as a variant of the Baaz projection. The main difference is that although our new $\Delta$ satisfies many properties of Baaz projection, it can nether be interpreted as Baaz's projection itself nor its generalizations. For this, we first introduce several weakening-free fuzzy logics with the alternative connective $\Delta$. The algebraic structures corresponding to the systems are then defined, and their algebraic completeness is proved.

• Proceedings of the Korea Water Resources Association Conference
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• 2017.05a
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• pp.95-99
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• 2017

서낙동강 하류에 국내 최초로 친수구역 활용에 관한 특별법에 따른 부산 에코델타시티(Eco Delta City, EDC) 조성사업이 시행 중에 있으며, 친수공간 확보 및 친수활동에 대한 관심의 증가로 서낙동강 수질개선에 대한 필요성이 증가하고 있다. 이에 부산 EDC 사업에서는 친수활동을 위한 목표 수질(II급수)을 설정하고 목표수질을 달성하기 위해 EFDC 모형을 활용하여 서낙동강 유역의 수질개선 방안을 검토하였다. 서낙동강 유역의 하수처리 정비 등을 통한 오염부하의 삭감, 부산 EDC 사업의 오염부하 삭감 및 서낙동강, 평강천, 맥도강 물순환 등의 대책을 통하여 목표 수질을 달성할 수 있을 것으로 연구되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.