• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.174-178
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• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.6
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• pp.491-496
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• 2005

In this paper, test on characteristics of 3-phase line-interactive UPS system, known as delta conversion UPS system, is studied. Delta conversion UPS system is new line-interactive UPS system using two series-parallel PWM converters instead of using series inductor in conventional single conversion line-interactive UPS system. It is known that the characteristics of input and output in delta conversion UPS system is much improved by controlling source current of AC lines directly. Here the results on load test, normal/backup mode test, and normal/bypass mode test, which are very important in the test on characteristics of UPS system, is presented. And finally overall evaluation on delta conversion UPS system is given.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.72-76
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• 2004

본 논문에서는 일명 델타변환 무정전전원장치(UPS)로서 알려져 있는 3상 라인 인터랙티브 UPS 시스템의 성능 시험에 대해서 다루고 있다. 델타변환 UPS는 종래의 단일 변환 라인 인터랙티브 UPS 시스템에서 직렬 인덕터를 제거하고 직렬 및 병렬 PWM 컨버터를 사용하는 새로운 라인 인터랙티브 UPS 시스템으로 전원 전류를 직접 제어함으로써 UPS 시스템의 입출력 특성들이 상당히 개선되는 것으로 알려져 있다. 여기서는 UPS 시스템의 성능 시험에서 중요한 내용들인 부하시험, 정전/복전시험, 동기절체 시험 등에 대한 결과들을 제시하고 델타변환 UPS 시스템에 대한 전반적인 평가를 한다.

• Journal of IKEEE
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• v.17 no.3
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• pp.234-240
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• 2013

This paper presents an incremental delta-sigma analog-to-digital converter (ADC) for a single-electrode capacitive touch sensor. The second-order cascade of integrators with distributed feedback (CIFB) delta-sigma modulator with 1-bit quantization was fabricated by a $0.18-{\mu}m$ CMOS process. In order to achieve a wide input range in this incremental delta-sigma analog-to-digital converter, the shielding signal and the digitally controlled offset capacitors are used in front of a converter. This circuit operated at a supply voltage of 2.6 V to 3.7 V, and is suitable for single-electrode capacitive touch sensor for ${\pm}10-pF$ input range with sub-fF resolution.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.225.1-225.1
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• 2013

지난 수년간 태양전지의 광전변환 효율을 높이기 위해 자가 조립된 InAs 또는 GaSb 와 같은 양자점을 GaAs 단일 p-n 접합에 적용하는 연구를 개발해 왔다. 그러나 양자점의 흡수 단면적에 의한 광흡수도는 양자점층을 수십 층을 쌓으면 증가하지만 활성층에 결함을 생성시킨다. 생성된 결함은 운반자 트랩으로 작용하여 태양전지의 광전변환 효율을 감소시킨다. 본 실험에서는 양자점이 적용된 태양전지와 적용되지 않은 태양전지의 광전변환 효율을 비교하고, 깊은준위 과도용량 분광법을 이용하여 결함상태를 측정하고 및 비교함으로써, 활성층 내부에 생성된 결함이 광전변환 효율에 미치는 영향을 분석하였다. 소자구조는 분자선 증착 방법을 이용하여, 먼저 n-형 GaAs 기판위에 n-형 GaAs를 300 nm 증착한 후, 도핑이 되지 않은 GaAs 활성층을 3.5 ${\mu}m$ 두께로 증착하였다. 마지막으로 p-형 GaAs를 830 nm 증착함으로써 p-i-n구조를 형성하였다. 여기서, n-형 GaAs 과 p-형 GaAs의 도핑농도는 동일하게 $5{\times}1018\;cm^{-3}$ 로 하였다. 또한 양자점 및 델타도핑 층을 각각 태양전지에 적용하기 위해 활성층내에 양자점 20층 및 델타도핑 20층을 각각 형성하였다. 이때, 양자점 태양전지, 델타도핑 태양전지와 양자점이 없는 태양전지의 광전변환 효율은 각각 4.24, 4.97, 3.52%로 나타났다. 태양전지의 전기적 특성을 측정하기 위해 소자구조 위에 Au(300nm)/Pt(30nm)/Ti(30nm)의 전극을 전자빔 증착장치로 증착하였으며, 메사에칭으로 직경 300 ${\mu}m$의 p-i-n 접합 다이오드 구조를 제작하였다. 정전용량-전압 특성 및 깊은준위 과도용량 분광법을 이용하여 태양전지의 결함분석 및 이에 따른 광전변환 효율의 상관관계를 논의할 것이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.104-110
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• 2006

The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1887-1894
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• 2010

This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.