• Journal of Korea Game Society
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• v.7 no.3
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• pp.31-38
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• 2007

In this paper, we proposed an effective visibility test architecture with improving the mid-texturing architecture. The proposed architecture uses the property of fragments that the visibility of adjacent fragments is identical, and performs only a single visibility test per fragment. To compare with the mid-texturing architecture, simulation results show that the bandwidth requirements and the cell area of the depth cache in the proposed architecture are reduce by 25% and 34%, respectively, in exchange for less than 5% performance decline.

• KIISE Transactions on Computing Practices
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• v.23 no.12
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• pp.691-697
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• 2017

Volcanic ash has been predicted to be the main source of damage caused by a potential volcanic disaster around Mount Baekdu and the regions of the Korean peninsula. Computer simulations to predict the diffusion of volcanic ash should be performed according to prevalent meteorological situations within a predetermined time. Therefore, a workflow using pipelining is proposed to parallelize the software used for this computation. Due to the nature of volcanic calamities, the simulations need to be carried out for various plausible conditions given that the parameters cannot be precisely determined during the simulations, even at the time of a volcanic eruption. Among the given conditions, computations need to be first performed for the condition with the highest probability so that a response to the volcanic disaster can be provided using these results. Further action can then be performed later based on subsequent results. The computations need to be performed using a volcanic disaster damage prediction system on a computing server with limited computing performance. Hence, an optimal distribution of the computing resources is required. We propose a method through which specific data can be provided first to the proposed pipeline-based workflow.

• Journal of KIISE
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• v.42 no.8
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• pp.1010-1021
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• 2015

Big data systems are widely used to collect large-scale log data, so it is very important for these systems to operate with a high level of performance. However, the current Hadoop-based big data system architecture has a problem in that its performance is low as a result of redundant processing. This paper solves this problem by improving the design of the Hadoop system architecture. The proposed architecture uses the batch-based data collection of the existing architecture in combination with a single processing method. A high level of performance can be achieved by analyzing the collected data directly in memory to avoid redundant processing. The proposed architecture guarantees system expandability, which is an advantage of using the Hadoop architecture. This paper confirms that the proposed architecture is approximately 30% to 35% faster in analyzing and processing data than existing architectures and that it is also extendable.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.119-126
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• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level

• The Transactions of the Korea Information Processing Society
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• v.5 no.7
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• pp.1691-1716
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• 1998

본 논문에서는 계층적 블록매칭 알고리즘(HBMA)을 위한 두 가지 병렬 VLSI 아키텍쳐를 제안한다. HBMA는 계층에 따른 반복수행과 공간 인터폴레이션을 기반으로 수행되며, 이러한 수행 특성은 병렬처리의 장애요소인 데이터 종속성을 내재하고 있다. 제안된 아키텍쳐는 HBMA의 계층간 데이터 종속성을 해결하기 위하여 기본적으로 파이프라인 구조를 채택하고 있으며, HBMA에서 주어진 매개변수에 따라 세 단계의 스테이지로 구성된다. 제안된 아키텍쳐는 입력 프레임 데이터의 흐름을 제어하는 방식에 따라 두 가지 종류로 구분된다. U-Architecture는 단방향 스캔 순서를 따르도록 설계되었으며, B-Architecture는 양방향 스캔 수서를 따르도록 설계되었다. 각 아키텍쳐의 내부 메모리와 인터폴레이션 모듈은 해당 스캔 순서에 따라 동기적으로 동작할 수 있는 구조를 가진다. 성능분석의 결과로서 본 논문에서 제안한 두 가지 아키텍쳐가 모두 방송용 비디오 포맷을 실시간으로 처리할 수 있음을 보이고, HDTV 포맷은 가까운 장래의 VLSI 기술로 실시간 성능을 얻을 수 있음을 보였다. 또한, B-Architecture는 공간 연결성 내부 메모리 구조를 채택함으로써 입력 데이터의 재활용도를 높이고, 이에 따라 Q-Architecture에 비해서 데이터 입출력 핀의 개수를 약 반정도 줄일 수 있는 특성을 보이고 있다.

• The Bulletin of The Korean Astronomical Society
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• v.33 no.2
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• pp.27.2-27.2
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• 2008

• Annual Conference on Human and Language Technology
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• 2018.10a
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• pp.343-346
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• 2018

기존의 의미역 결정은 먼저 구문 분석을 수행한 후에 해당 구문 분석 결과를 이용해 의미역 결정 테스크에 적용하는 파이프라인 방식으로 진행한다. 이러한 방식의 학습을 두 번 연이어 진행하기 때문에 시간이 오래 걸리고 또한 구문 파싱과 의미 파싱에 대해 서로 영향을 주지 못하는 단점이 존재하였다. 본 논문에서는 의존 파싱과 의미역 파싱을 동시에 진행하도록 전이 액션을 확장한 의존 파싱 & 의미역 결정 통합 모델을 제안하고 실험 결과, Korean Prop Bank 의미역 결정 데이터 셋에서 파이프라인 방식 전이 기반 방식을 사용한 모델보다 논항 인식 및 분류(AIC) 성능에서 F1 기준 0.14% 높은 결과을 보인다.

• Journal of the Korean Society for Marine Environment & Energy
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• v.19 no.1
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• pp.52-61
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• 2016

To inject huge amount of $CO_2$ for CCS application, high pressure pipeline transport is accompanied. Rapid depressurization of $CO_2$ pipeline is required in case of transient processes such as accident and maintenance. In this study, numerical analysis on the depressurization of high pressure $CO_2$ pipeline was carried out. The prediction capability of the numerical model was evaluated by comparing the benchmark experiments. The numerical models well predicted the liquid-vapor two-phase depressurization. On the other hands, there were some limitations in predicting the temperature behavior during the supercritical, liquid phase and gaseous phase expansions.