• Journal of the Computational Structural Engineering Institute of Korea
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• v.37 no.2
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• pp.103-110
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• 2024

In this study, a nonlinear dynamic analysis of a frame and single member, which reflect the characteristics of a plant facility, is performed using the commercial MIDAS GEN program and the results are analyzed. The general structural members and material properties of the plant are considered. The Newmark average-acceleration numerical-analysis method is applied to a plastic hinge to study material nonlinearity. The blast load of a vapor-cloud explosion, a representative plant explosion, is calculated, and nonlinear dynamic analysis is conducted on a frame and single member. The observed dynamic behavior is organized according to the ratio of natural period to load duration, maximum displacement, ductility, and rotation angle. The conditions and range under which the frame functions as a single member are analyzed and derived. NSFF with a beam-column stiffness ratio of 0.5 and ductility of 2.0 or more can be simplified and analyzed as FFC, whereas NSPF with a beam-column stiffness ratio of 0.5 and ductility of 1.5 or more can be simplified and analyzed as FPC. The results of this study can serve as guidelines for the blast-resistant design of plant facilities.

• Journal of Life Science
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• v.24 no.7
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• pp.707-712
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• 2014

We evaluated the phenetic relationships within six taxa of genus Oxalis L. in Korea with random amplified polymorphic DNA (RAPD) markers. Ten primers produced 125 bands for six taxa, and the mean number of bands per primer was 12.5. Across the six taxa, 121 (96.8%) bands were polymorphic, and only four were monomorphic. The mean number of RAPD phenotypes across the six taxa varied from 3.6 (O. stricta and O. corymbosa) to 4.8 (O. corniculata for. rubrifolia). In a simple measure of intraspecies variability according to the percentage of polymorphic bands, O. stricta and O. corymbosa exhibited the lowest variation (28.8%), and O. corniculata for. rubrifolia showed the highest (38.4%). A mean of 32.7% of the loci was polymorphic within taxa. The total interspecies genetic diversity ($H_T$) and intraspecies genetic diversity ($H_S$) was 0.362 and 0.122, respectively. On a per-locus basis, the proportion of total genetic variation due to differences among species ($G_{ST}$) was 0.663. This indicates that about 66.3% of the total variation was among species. The node of O. stricta and O. corniculata for. rubrifolia was strongly supported, with a high bootstrap value in the NJ tree and sistered with O. corniculata. According to RAPD analysis, the number of chromosomes was not congruent with a phenetic relationship.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of KIISE
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• v.44 no.4
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• pp.383-391
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• 2017

As we enter a new era of Big Data, the amount of semantic data has rapidly increased. In order to derive meaningful information from this large semantic data, studies that utilize the SWRL(Semantic Web Rule Language) are being actively conducted. SWRL rules are based on data extracted from a user's empirical knowledge. However, conventional reasoning systems developed on single machines cannot process large scale data. Similarly, multi-node based reasoning systems have performance degradation problems due to network shuffling. Therefore, this paper overcomes the limitations of existing systems and proposes more efficient distributed inference methods. It also introduces data partitioning strategies to minimize network shuffling. In addition, it describes a method for optimizing the incremental reasoning process through data selection and determining the rule order. In order to evaluate the proposed methods, the experiments were conducted using WiseKB consisting of 200 million triples with 83 user defined rules and the overall reasoning task was completed in 32.7 minutes. Also, the experiment results using LUBM bench datasets showed that our approach could perform reasoning twice as fast as MapReduce based reasoning systems.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.959-968
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• 1999

several papers have reported that parallel heuristics or hybrid approaches combining several heuristics can get better results. However, the parallelization and hybridization of any search methods on the single CPU type computer need enormous computation time. that case, we need more elegant combination method. For this purpose, we propose Fast Model of Parallel Heuristics(FMPH). FMPH is based on the island model of parallel genetic algorithms and takes local search to the elite solution obtained form each island(sub group). In this paper we introduce how can we adapt FMPH to the job-shop scheduling problem notorious as the most difficult NP-hard problem and report the excellent results of several famous benchmark problems.

• The Korean Journal of Applied Statistics
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• v.31 no.5
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• pp.539-554
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• 2018

Effective interaction between user and device is considered an important ability of IoT devices. For some applications, it is necessary to recognize human facial expressions in real time and make accurate judgments in order to respond to situations correctly. Therefore, many researches on facial image analysis have been preceded in order to construct a more accurate and faster recognition system. In this study, we constructed an automatic recognition system for facial expressions through two steps - a facial recognition step and a classification step. We compared various models with different sets of data with pixel information, landmark coordinates, Euclidean distances among landmark points, and arctangent angles. We found a fast and efficient prediction model with only 30 principal components of face landmark information. We applied several prediction models, that included linear discriminant analysis (LDA), random forests, support vector machine (SVM), and bagging; consequently, an SVM model gives the best result. The LDA model gives the second best prediction accuracy but it can fit and predict data faster than SVM and other methods. Finally, we compared our method to Microsoft Azure Emotion API and Convolution Neural Network (CNN). Our method gives a very competitive result.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.1-13
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• 1999

As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.59-66
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• 2000

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

• Journal of KIISE:Software and Applications
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• v.36 no.7
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• pp.590-606
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• 2009

We present a static analyzer that detects memory leaks in C programs. It achieves relatively high accuracy at a relatively low cost on SPEC2000 benchmarks and several open-source software packages, demonstrating its practicality and competitive edge against other reported analyzers: for a set of benchmarks totaling 1,777 KLOCs, it found 332 bugs with 47 additional false positives (a 12.4% false-positive ratio), and the average analysis speed was 720 LOC/sec. We separately analyze each procedure's memory behavior into a summary that is used in analyzing its call sites. Each procedural summary is parameterized by the procedure's call context so that it can be instantiated at different call sites. What information to capture in each procedural summary has been carefully tuned so that the summary should not lose any common memory-leak-related behaviors in real-world C program. Because each procedure is summarized by conventional fixpoint iteration over the abstract semantics ('a la abstract interpretation), the analyzer naturally handles arbitrary call cycles from direct or indirect recursive calls.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.573-581
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• 2002

In this paper, we propose a mediaprocessor of dual-cache architecture which is composed of the multimedia data cache and the general-purpose data cache to prevent performance degradation caused by memory delay. In the proposed processor architecture, multimedia data that are written in subword instructions are loaded in the multimedia data cache and the remaining data are loaded in the general-purpose data cache. Also, Ive use multi-block prefetching scheme that fetches two consecutive data blocks into a cache at a time to exploit the locality of multimedia data. Experimental results on MPEG and JPEG benchmark programs show that the proposed processor architecture results in better performance than the processor equipped with single data cache.